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Questions tagged [gtkwave]

GTKWave is an open-source wave visualization software which is compatible with many known wave formats, including wif (created by modelsim). It is commonly used to visualize the testbench output of VHDL/Verilog implementations.

More information is available at the GTKWave site.

27 questions
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Reload VCD file in gtkwave from command line

I am using a VCD file generated by iverilog with gtkwave. There is a button present in the GUI, but I would like to reload the wave window from the command line. How would I go about that?
user7426532
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gtkwave tcl script for adding specific signals

I have a huge VCD file that I use in combination with gtkwave to observe certain signal behaviors. I have a list of signals stored into a .txt file which are the ones that I wish to probe. The thing is that by doing the insertion of the signals…
ex1led
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GTKW Unable to block on application (GHDL macos)

I am able to successfully analyze and run a simple VHDL counter in GHDL on macos, but when launching GTKW, the use of a generic causes problems. The error message is Unable to block on application (GetProcessPID() returned 184467095516) Any ideas…
P2000
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generate register delay for simulation in chisel

When I am using Verilog, I would like to define a register like this: reg [7:0] cnt; always @ (posedge clk) begin cnt <= #1 cnt + 1; end Because of using #1, the register will change a little bit behind the clk posedge in the waveform, and it…
DDK
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How do I measure time between two markers in gtkwave?

I am simulating my verilog design using iverilog and dump the output to an fst file. I am then using gtkwave to view the waveform. gtkwave allows me to add a number of markers. How do I then measure the delta between any two markers. I read through…
Prashant
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How can I check the difference between sc_buffer and sc_signal?

I would like to check the difference between using sc_buffer and sc_signal. I have coded a module which adds two random numbers and then I run two tests in parallel: one using sc_buffer and the other using sc_signal. Nevertheless, when I check with…
Marco
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Error opening .vcd file. No such file or directory

My Verilog code is stored in C:\FA. There are three files: FA.v, fa.vvp, TM_FA.v I followed my book steps. iverilog -o fa.vvp vvp fa.vvp finish getwave fa.vcd & When I use getwave fa.vcd & to simulate it, and then it shows: Error opening .vcd…
Kias
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Could not initialize GTK! Is DISPLAY env var/xhost set? on Debian WSL

I'm trying to use a file "testar.sh" to test GHDL and GTKWave installation on Debian, that's the command I should use: chmod +x testar.sh; ./testar.sh, then this is what its shown Could not initialize GTK! Is DISPLAY env var/xhost set? Usage:…
C0d3Bl0cks
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vhdl and gate returning unknown value

I was implementing a multiplexer, but and gate returning "x" for no reason, pls help. As you can see in screenshot, result just became "x" from "1". i did a testbench for and gate, it works fine on its own. It should have been a 3 bit 4:1…
Tawpik Talat
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Verilog garbage input does not result in garbage output

I am writing a simple Control Unit in verilog. It goes something like this. module controlUnit( output reg wreg, input wire [5:0] op, func ); // wreg sub-handles. Beware: wreg is 0 if any of these s high wire isBranch = (op[5:3] ==…
Kraken
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Problems with GHDL compilation

I am new to GHDL software.After downloading ghdl for windows I checked a simple half adder program. while using the command ghdl -e ha_tb ghdl -r ha_tb I am getting an error like this... ghdl.exe: Cannot find entity or configuration ha_tb Ghdl…
RISCV
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String pattern matching with tcl

I am new to tcl and am trying to only capture a user-specified hierarchy depth of the following: top.run.end top.run.something.end top.simple.end1 …
nichollsg
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How to change timescale in vcd generated by chisel3 iotester

I already asked a similar question for chisel2 in case of C++ backend. But now I'm using The template example with iotester (peek and poke) with chisel3. With the following code (can be found on my github project page): class TapTempoUnitTester(t:…
FabienM
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GtkWave isn't getting signals from IVerilog simulation

I wrote the following test for my code: module HalfAdder_Test; wire sum; wire carry; reg a = 0; reg b = 0; initial begin $dumpfile("test.vcd"); $dumpvars(0, HalfAdder_Test); # 10 a = 0; # 10 b = 0; # 30 a = 1; # 30 b =…
Tyler Hilbert
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signal drops to undefined while all related signals are defined

I am writing a process that has to look for every incoming bit, keep track of wether or not the total amout of ones received is 1 and, when the time comes has to compare the value to a reference value. The process is the following: parity_tester :…
Cheiron
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