Unable to read data input file in verilog

Question

I am trying to read the data from external file named "data.in" in verilog rest bench. I am trying to store data from the file in two variables, data1 and data2. Here is some part of the input file. Only hex data is to be read. No need to read the comments.

// This is a generated input file.
//
//  rj
// Left      Right        No.
   003E      002E      // r1
   002E      0017      // r2
   0026      0030      // r3
   0005      002C      // r4
   0034      0015      // r5
   000B      0023      // r6
   0007      0021      // r7
   0028      0001      // r8
   0007      0012      // r9
    //
//  Coefficient u
   00D3      0034      // 1
   0116      01F2      // 2
   0016      0154      // 3
   01D0      002E      // 4

I have already tried memread, fscanf but no luck. any help is great. thanks in advance.

Try using $readmemh. You can have look at this question http://stackoverflow.com/questions/628603/readmemh-writememh-related-resources for more details. — ssgr, Oct 16 '15 at 06:39
Thanks @ssgr for your help, I have already tried that but using $readmemh, I am not getting the data from single line, it access entire file as a single string. — Virbhadra Rathod, Oct 16 '15 at 06:53

score 1 · Accepted Answer · answered Oct 16 '15 at 09:11

Unless you have restrictions that prevent you from doing so, the easiest way is to use $readmemh into a single variable and split the data as needed afterwards:

  reg [15:0] data[26]; // Make this is total number of 16-bit values to read from the file
  reg [15:0] data1[13]; // Also make these as long as needed, which I assume they are already
  reg [15:0] data2[13];
  integer i;  
  ...
  initial begin
    $readmemh("data.in", data);
    for (i = 0; i < 26; i  = i + 1) begin
      if (i % 2) begin // Right
        data2[i / 2] = data[i];
      end
      else begin // Left
        data1[i / 2] = data[i];
      end
    end
  end

The above will left you read the data into arrays with the right and left data split. You can always skip that step knowing the left data is in even numbered elements of data and right data is in odd numbered elements.

Unable to read data input file in verilog

1 Answers1