creating a 4Kb Data structure in systemverilog

Question

score 1 · Answer 1 · answered Oct 16 '15 at 10:10

use, struct type in SystemVerilog.

for example 512 bite data structure of 128 bit,

struct { 
   bit [127:0] part1; 
   bit [127:0] part2;
   bit [127:0] part3;
   bit [127:0] part4;
} largePart_512;

Note that, you have to access this struct with largePart_512,

part1 - largePart_512[127:0]

part2 - largePart_512[255:128]

part3 - largePart_512[383:256]

part4 - largePart_512[511:384]

score 0 · Answer 2 · answered Oct 16 '15 at 10:13

0

Create a memory with each word as 128 bits and the depth equal to 4096/128:

logic [127:0] mem [4096/128];

answered Oct 16 '15 at 10:13

nguthrie

1

Will this be contiguous memory? I doubt, since there is an unpacked side in it. Will it be better to use `logic [4096/128][127:0] mem;` or something like that? – sharvil111 Oct 16 '15 at 11:18
1

@sharvil111 No, the above is not guaranteed to be contiguous in memory. But from the OP, there is no need for this requirement unless they need to access more than one 128-bit word in a single assignment. Typically to represent memories, you use packed vectors for everything except the memory size, which is unpacked (though you can also do banking or such that would also be unpacked). See this answer for reasons for this: http://stackoverflow.com/questions/511542/why-should-i-use-unpacked-vectors-in-system-verilog – Unn Oct 16 '15 at 11:43
Note that Im not sure which is faster in simulation, maybe dave_59 or others know (I would test it but my EDAplayground is being silly) – Unn Oct 16 '15 at 11:45
Yep, the bit-bleeding explanation on that link seems to be quite sound. Thanks for help @Unn. Still I think, packed arrays may be faster in simulations; just a personal feeling no technical evidence. – sharvil111 Oct 17 '15 at 05:15

2 Answers2