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I am having trouble making testbenches. It is far into the quarter in my school but I feel like I am missing out on some fundamentals.

Here I am trying to make a 2 by 4 decoder, but I want to simulate it inside verilog. 

module decoder2to4(x, enable, y);

input [1:0] x; //this is my decoder input 
input enable;
output [3:0] y; 

reg [3:0] y; 

always @(x, enable ) //
begin

    if(enable==0)   //if enable isn't on, all outputs WON'T OUTPUT correct and give us 1111
        y = 4'b1111; 
    else //if enable is high...
        if (x == 2'b00) //...then we check our inputs and give corresponding outputs 
            y = 4'b0001; 
        if (x == 2'b01)
            y = 4'b0010; 
        if (x == 2'b10)
            y = 4'b0100; 
        if (x == 2'b11); 
            y = 4'b1000;
     end
endmodule

This is my simulation file ~ did i write it correctly ? 

module testbench_2to4decoder;

reg [1:0] x; //use reg not wire to assign values

wire [3:0] y; //for the outputs 

2to4Decoder uut(x,y); 



initial begin

    x = 2'b00; 
    enable = 1'b0; //keep it off
    #10 //wait some time

    enable = 1'b1; //turn enable on
    #10; //wait some time

    x = 2'b01; //input 01
    #10;  //wait some time
    x = 2'b10; //input 10
    #10;        //then
    x = 2'b11; //input 11
    #10; 
    enable = 1'b0; //turn it off
    #10; 
    end 


endmodule
Morten Zilmer
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Kenny Truong
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  • In module `decoder 2to4` it is better paractise to use an automatic sensitivity list instead of manual, ie `always @*` instead of `always @(x, enable )`. Instead of cascaded if statements a case statement gives cleaner code. – Morgan Nov 17 '15 at 15:43

1 Answers1

2

You are not instantiating the design properly. Firstly, enable is not connected. enable is not even declared in testbench.

Also, the module name is wrong. Instead of following:

2to4Decoder uut(x,y);

You must have: 

decoder2to4 uut(x,enable, y);

Using a reset logic is encouraged to have default values of output. But since this is a combinational circuit, it is not mandatory here.

The inputs can be provided by using a for or repeat loop and increment variable x in it. But this is just for coding efficiency.

Rest of the things seems to be fine. Refer Module instantiation link.

Community
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sharvil111
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  • ahh silly me, I named my module different than what i instantiated it with. Thanks for catching that. – Kenny Truong Nov 16 '15 at 10:30
  • I've made changes but it still won't work. I tried to also add an input enable in the test fixture but it won't simulate. – Kenny Truong Nov 16 '15 at 10:31
  • `timescale 1ns / 1ps module testbench_2to4decoder; reg [1:0] x; //use reg not wire to assign values wire [3:0] y; //for the outputs decoder2to4 uut(x,y, enable); initial begin x = 2'b00; enable = 1'b0; //keep it off #10 //wait some time enable = 1'b1; //turn enable on #10; //wait some time x = 2'b01; //input 01 #10; //wait some time x = 2'b10; //input 10 #10; //then x = 2'b11; //input 11 #10; enable = 1'b0; //turn it off #10; end endmodule – Kenny Truong Nov 16 '15 at 10:31
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    I simulated your code [here](http://www.edaplayground.com/x/Pcx), I added **enable** signal, refer to the link. – sharvil111 Nov 16 '15 at 10:37