Write followed by Read in VHDL process

Question

The following code is for a very simple program in VHDL.

entity ent is
    port(
        clk: in std_logic;
        out_value: out std_logic;
    );
end entity ent;

architecture ent_arch of ent is
    signal counter: std_logic_vector(3 downto 0);
begin
    process(clk)
    begin
        if rising_edge(clk) then
            counter <= counter + 1;
            if counter = 10 then
                counter <= (others => '0') ;
            end if;
        end if;
    end process;
end ent_arch;

Imagine counter = 9 and we enter in the if statement (if rising_edge(clk)). The first statement counter <= counter + 1 will assign 10 to counter. My question is "Is the if statetement (if counter = 10) evaluted as true in this entrance or in the next entrance of the process?". In other words "For this comparison in this entrance of the process, is counter = 10 due to the previous statement?"

Thanks a lot for any answer!

Answered many places ... including here. http://stackoverflow.com/questions/13954193/is-process-in-vhdl-reentrant/13956532#13956532 — , Nov 23 '15 at 16:10
Variables values are immediately available while signals are scheduled for update in a projected output waveform queue. There's an implicit 'after 0 fs' after a signal assignment and any secondary unit is legal for 0 with any resolution limit. The value of counter will be available in the next simulation cycle the process is active. Instead, `iif counter = 9 then counter <= (others => '0'); else counter <= counter +1; end if;` When it's 9 set to zero, else increment. — , Nov 23 '15 at 18:16

score 0 · Answer 1 · answered Apr 03 '16 at 17:37

Signal assignments are always delayed. You didn't specified a delay explicitly using the after keyword, thus the assignment is delayed for one delta cycle (same as after 0 fs). That means, that the value of the expression on the right side of this statement:

counter <= counter + 1;

will be assigned to counter at the beginning of the next simulation cycle.

But, all remaining statements in your process, are executed in the current simulation cycle. Thus, this read of the counter value,

if counter = 10 then

will still use the old value, so that, the counter will be reseted when it is already 10 at the rising clock edge. The counter counts from 0 to 10 inclusive.

The delay of at least one delta cycle, easily allows to swap the content of registers:

-- within declarative part of architecture
signal reg_a, reg_b : std_logic;

-- within architecture body
process(clock)
begin
  if rising_edge(clock) then
    reg_a <= reg_b;
    reg_b <= reg_a;  -- assign old value of reg_a ! 
  end if;
end process;

Write followed by Read in VHDL process

1 Answers1

Linked