-4
module myfunction();
    function [31:0] myfunction;
            input [31:0] a;
            localparam bytes = 4;
            begin
              for(i=0; i<4;i= i+1)
              begin
                myfunction[8*i + 7: 8*i] = input[(3 - i*8) + 7 :   (3 -i)*8];
              end
    endfunction
endmodule

I am getting error of malformed statement on line myfunction in for loop. I am very new to verilog. Please help me with the error

Morgan
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user3509540
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2 Answers2

2

As @alex.forencich showed, bit-slicing is to be done by +: operator since you have non-constant slicing index.

Also, input is a SystemVerilog keyword. So, change of variable name is required here. i needs to be declared. The following snippet is compiled version of your code.

module myfunction_mod();
    function [31:0] myfunction;
            input [31:0] a;
           // Dummy input1 declared for sample
            reg [31:0] input1;
            localparam bytes = 4;
            begin
              for(int i=0; i<4;i= i+1) // declare i
              begin
               // Note input1 here
               myfunction[8*i +: 8] = input1[8*(3-i) +: 8];
               // Else use a here
               // myfunction[8*i +: 8] = a[8*(3-i) +: 8];
              end
            end
    endfunction
endmodule

This shall solve the compile error. One more comment from my side, keep different function name and module name as far as possible. This shall help in hierarchy issues.

Refer to this and this links for bit-slicing.

Community
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sharvil111
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1

I'm not sure exactly what error you're getting here. However, I would recommend using the indexed part select style like so:

myfunction[8*i +: 8] = input[8*(3-i) +: 8]

You should also make sure all of your begins and ends are matched up.

alex.forencich
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