I'm getting an error while using sll

Question

The problem is that I wanna use this sll command but am getting this error (in the pic). I know the

bp := bp(0 to 6) & '0';

statement, but I still wanna use this sll. Can anyone help?

Error line: 5th from the last

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std;

entity mul is
  port(
    a, b : in  std_logic_vector(0 to 3);
    c    : out std_logic_vector(0 to 7));
end mul;

architecture mul of mul is
begin
  process(a, b)
    variable bp, p : std_logic_vector(0 to 7);
  begin
    bp := "0000"&b;
    p  := "00000000";

    for k in 0 to 3 loop
      if a(k) = '1' then
        p := p + bp;
      end if;
      bp := bp sll 1;
    end loop;
    c <= p;
  end process;
end mul;

The error you received isn't in evidence here. If you have access to a -2008 compliant VHDL tool, substituting a use clause containing IEEE package numeric_std_unsigned for use clauses containing Synopsys package std_logic_arith and IEEE package numeric_std would allow your code to analyze, elaborate and simulate (without commenting on it's accuracy). Package numeric_std_unsigned allows you to treat std_logic_vector objects as if they were unsigned. — , Dec 06 '15 at 21:22
Possible duplicate of [shift a std\_logic\_vector of n bit to right or left](http://stackoverflow.com/questions/9018087/shift-a-std-logic-vector-of-n-bit-to-right-or-left) — Martin Zabel, Dec 06 '15 at 21:27

Morten Zilmer · Answer 1 · 2015-12-06T19:27:35.767

1

Mixing the non-standard VHDL (Synopsys) std_logic_unsigned package and the standard VHDL numeric_std package is likely to lead to undesired results, so my suggestion is to use only the standard VHDL numeric_std package using only:

use ieee.numeric_std.all;

With this you can then do:

if a(k) = '1' then
  p := std_logic_vector(unsigned(p) + unsigned(bp));
end if;
bp := std_logic_vector(unsigned(bp) sll 1);

The "sll" function from numeric_std package is then used as infix operator, and this is the same as writing:

bp := std_logic_vector("sll"(unsigned(bp), 1));

Note that for a shift amount of 1, it is the same as writing:

bp := std_logic_vector(shift_left(unsigned(bp), 1));

The last statement using the shift_left function is suggested, since the sll operator in VHDL may not always work as "expected" before VHDL-2008 (read more here), so using the shift_left function from the numeric_std package ensures readability and expected operation across different VHDL versions.

edited Dec 06 '15 at 19:27

answered Dec 06 '15 at 18:48

Morten Zilmer

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Or use IEEE package numeric_std_unsigned instead, for a -2008 compliant tool chain. – Dec 06 '15 at 21:23
@user1155120: How come `sll` or `shl` is not defined in `numeric_std_unsigned` for `(std_logic_vector, integer)`? Only `shl(std_logic_vector, std_logic_vector)` is defined. – Morten Zilmer Dec 06 '15 at 22:12
1

In -2008, std_logic_vector is a subtype of std_ulogic_vector and std_logic_1164 declares sll and srl for [std_ulogic_vector, integer return std_ulogic_vector]. – Dec 06 '15 at 22:39

I'm getting an error while using sll

1 Answers1