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I'm not that familiar in Verilog but can you call another module when it's inside a case statement?

George Netu
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Mamalagerz
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  • A somewhat similar question on this [link](http://stackoverflow.com/questions/33719071/error-while-using-always-block-in-verilog/33719290). You can have generate block also. – sharvil111 Jan 19 '16 at 13:28

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You cannot call a module just as you do in C language, since it's not a function, you instantiate it. If you want to instantiate a module, you should use generate.

Edit: An example of using generate with a case statement can be found here.

2nd edit: If you just wanted to call a section of code in a case-statement then you can create a task or a function. More information here. (credit goes to Hida)

Community
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George Netu
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  • To add to this: If you just wanted to call a section of code in a case-statement then you can create a task or a function. More information [here](http://www.asic-world.com/verilog/task_func1.html). – Hida Jan 21 '16 at 08:22
  • Indeed. If you don't mind, I can append it to the answer. – George Netu Jan 21 '16 at 11:32
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you can not call module within case statement , but you can create function and then call in case statement (task is not synthesizeble)

Dixita Patel
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