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I read a lot about the difference between CISC and RISC architectures from different sources. One of the things that seemed to be agreed upon is that CISC is always used with Von Neumann whereas RISC is used with Harvard architecture. But I couldn't quite grasp the reason behind this classification.

ROMANIA_engineer
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YaserM
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2 Answers2

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There is no relations between Instruction Set (RISC and CISC) with architecture of the processor (Harvard Architecture and Von Neumann Architecture). Both instruction set can be used with any of the architecture.

Older ARM architecture used Von Neumann Architecture with RISC, and later with ARM9 they shifted to Harvard Architecture with RISC. Latest ARM processor uses much more advanced hybrid architecture.

Rishit Sanmukhani
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    Wow, I had assumed a "real" CPU from 1998 (not a pure DSP) would always just be [modified Harvard](http://en.wikipedia.org/wiki/Modified_Harvard_architecture) (i.e. split L1 caches). I'm really surprised that ARM9 had separate external busses. (But wikipedia points out that system designers could "connect at least part of the address space in von Neumann style", so it's not limited to being a pure Harvard architecture.) Thanks for pointing out that example. – Peter Cordes Nov 19 '16 at 20:51
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Von Neumann vs Harvard isn't a clearcut difference. Obviously a chip with separate memory busses for instruction and data is Harvard architecture. But the performance benefit of separate busses is greatly reduced when good caches are added.

If you take such a chip and add good caches, and then switch back to a single memory bus, where an extra pin indicates whether the memory fetch is for instruction or for data, you're still really talking about a Harvard architecture - and from a programming perspective, you can't tell that such a change has happened.

I think probably the biggest difference is that on a true Von Neumann CPU, you can write to the instruction memory, and then immediately execute the instructions you wrote. On an 8086, for example, you can write to the instruction immediately after the write instruction! Whereas on a Harvard CPU, even one with a unified memory bus, you'd have to follow the write with an instruction to force that write out to actual memory, possibly an instruction to prevent out-of-order execution, and then an instruction to flush the instruction cache at that location. This process can take several hundred cycles - and it's necessary because the architecture of the chip assumes that instruction and data memory don't interact.

This change can even take place within the same CPU family. The original cache-less 68000 is certainly a CISC CPU, but if you write to the instruction stream, you have to beware of the instruction prefetch, and potentially add a NOP after your write to memory. Later variations of the 680x0 family, however, became more and more Harvard-like. The external memory bus may have remained unified, but instruction and data caches were separate, for example.

jorgbrown
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  • Original 8086 actually could observe stale instruction fetch; it didn't snoop its 6-byte prefetch buffer. A jump worked to make it safe to execute recently-modified code. Modern x86 CPUs go beyond the on-paper requirement by snooping for stores to addresses in the pipeline. (So it is actually true you can't observe stale fetch; [a stronger guarantee is easier to implement on an out-of-order exec CPU](//stackoverflow.com/a/18388700/224132) than one just barely strong enough.) On paper I think a pipeline-serializing instruction is required, but de-facto it's well known that a jmp works. – Peter Cordes Jun 26 '20 at 07:55
  • A modified-harvard (split L1 caches, unified memory) only needs to commit stores and do an I-cache sync instruction like PowerPC `isync` to make it safe to execute stores as code. But a true Harvard machine (like AVR) with split address space would need an instruction like store-program-memory to store into that different address space. Your 2nd paragraph talks about true Harvard split address space, but then the next paragraph just talks about syncing caches, assuming that stores can write program memory at all. So you might want to tweak the wording for consistency. – Peter Cordes Jun 26 '20 at 08:00