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Questions tagged [risc]

DO NOT USE. Use the specific ISA that your question relates to instead, e.g. [arm], [mips], [riscv], [avr] or [instruction-set] for questions about instruction sets in general.

RISC systems are typically load/store in nature, whereby all instructions operate only on registers or immediate values, rather than memory. In order to work against memory the data must be loaded into a register or written from a register using memory specific instructions.

Some well known examples of RISC CPUs are ARM, MIPS, PowerPC, RISC-V and SPARC.

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Are PUSH/POP instructions considered RISC or CISC?

I was asked in an interview if PUSH and POP are RISC or CISC instructions. I said that they were RISC, but they told me that they were actually CISC instructions. I suggested that ARM (a common RISC implementation) has these instructions, but they…
user1998844
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Why are there two ways to multiply arbitrary signed numbers in MIPS?

If you need to multiply two arbitrary signed numbers in MIPS, is there a reason to prefer: mul $t0 $s0 $s1 Or this: mult $s0 $s1 mflo $t0 ? I'm finding inconsistent answers online with regard to what each one means. At first glance I would expect…
Adam Smith
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Indexed addressing mode and implied addressing mode

Indexed addressing mode is usually used for accessing arrays as arrays are stored contiguosly. We have a index register which gets incremented in every iteration which when added to base address gives the array element address. I don't understand…
Zephyr
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RISC under CISC ISA

I am learning about CPU architecture and it is bit confusing. Is it correct that old microprogrammed CISC CPUs would translate ISA instruction into series of simple (1 cycle) microinstructions?(and that by RISC philosophy ISA instruction basically…
Mr. Vader
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How many clock cycles do the stages of a simple 5 stage processor take?

A 5 stage pipelined CPU has the following sequence of stages: IF – Instruction fetch from instruction memory. RD – Instruction decode and register read. EX – Execute: ALU operation for data and address computation. MA – Data memory access – for…
curiousgeorge
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Why this MIPS loop stops printing strings while asking for integers

I'm trying to enter a 4x4 matrix by user input with some nice strings. Something makes one of the strings stop printing at the third iteration, and then the other string stops printing at iteration number 7. I thought it could be a MARS emulator bug…
ecomaikgolf
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assembly program for Fibonacci

I just got a question about the assembly program for Fibonacci sequence. The question is as following : The Fibonacci sequence F is defined as F(1) = F(2) = 1 and for n ≥ 2, F(n + 1) = F(n) + F(n − 1) i.e., the (n + 1)th value is given by the sum of…
hmmmmm_computing
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Why the RISC instruction sets usually do not contain register to register copy instruction?

I had this question on my exam and i am confused because as far as i know that move $t0, $a0 # COPY $A0 TO $T0 in MIPS instruction provides that and MIPS is a RISC processor. Am I missing something?
roffensive
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RISC - prohibited instruction sequences

The introduction to computer system book shows a difference between CISC & RISC as the following. CISC: Implementation artifacts hidden from machinelevel programs. The ISA provides a clean abstraction between programs and how they get…
kkpoker
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Why does this block of assembly code have 2 stalls in pipeline instead of 1?

To elaborate on the main question, why does the third line perform an execution a clock cycle after Register2 has already been written back? I was thinking it should only have 1 stall in the pipeline. But I am incorrect. Is it just some quality with…
Cristian G
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CISC and RISC architectures

I read a lot about the difference between CISC and RISC architectures from different sources. One of the things that seemed to be agreed upon is that CISC is always used with Von Neumann whereas RISC is used with Harvard architecture. But I couldn't…
YaserM
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Processor performance complex and simple instructions

I have been stuck on a problem in my class for a week now. I was hoping someone could help steer me in the right direction. a busy cat http://www.designedbychristian.com/unnamed.png Processor R IS A 64-BIT RISC processor with a 2GHz clock rate. The…
Christian4423
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Hand coded assembly - practical register allocation?

I've never written any long programs in assembly. But from my superficial experience it appears not as hard as people make it seem like. The only thing I can't quite wrap my head around is: How does one practically carry out register allocation?…
Michał B.
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Classic RISC pipeline- what does "memory access" stage actually do?

Referring to the wikipedia article: http://en.wikipedia.org/wiki/Classic_RISC_pipeline I am a little unsure what the "memory access" stage actually does. If "execute" actually does the execution, what purpose is there of retrieving memory addresses…
user997112
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DMA vs Load/Store Unit

As I understand The LSU(Load/Store Unit) in a RISC architecture like Arm handles load/store calls, and DMA(Direct Memory Access) Unit is responsible for moving data independent from the processor, memory to memory, peripheral to memory, etc. What I…
ALPEREN K
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