1

Now I'm trying to implement systemverilog tutorial here,

Especially, I am referring the switch tutorial of SystemVerilog.

If you view the code, they are used ordered port list in testcase TC(mem_intf, input_intf, output_intf[4]); but I want to change them to named port list. Does anyone know how to change into a named ordered port list from ordered port list in SystemVerilog?

dave_59
  • 39,096
  • 3
  • 24
  • 63
user5523035
  • 13
  • 5

2 Answers2

3

There can be four different types of port connections in SytemVerilog as follows:

(1) Using positional port connections. The one shown in your link code. The ports are mapped as per position in the instantiated module.

(2) Using named port connections. This is a verbose declaration. The position of ports does not matter. An example can be as follows. Note that the position can now be interchanged.

mymodule u1 (.data(data), .address(address));
// Is same as follows:
mymodule u1 (.address(address), .data(data));

(3) Using new SystemVerilog .name implicit port connections. Whenever the port name and size matches the connecting net or bus name and size, the ports get connected. This is not a widely used technique. 

// Searches for address and data sized variables in current module
mymodule u1 (.address, .data);

(4) Using new SystemVerilog .* implicit port connections. whenever the port name and size matches the connecting net or bus name and size, the ports are connected.

reg [2:0] address;
reg [15:0] data;
// Connect address data automatically. Provided the name is same.
mymodule u1 (.*);

So, in your case, the following are equivalent. Since the name of interface instances like input_intf, output_intf, and mem_intf are same, the .* connection shall also work.

testcase TC (.mem_intf(mem_intf),.input_intf(input_intf),.output_intf(output_intf));

testcase TC (.output_intf(output_intf),.mem_intf(mem_intf),.input_intf(input_intf));

testcase TC (.*);

For more information, refer to CummingsDesignCon2005_SystemVerilog_ImplicitPorts paper.

sharvil111
  • 4,301
  • 1
  • 14
  • 29
  • Thanks, can I ask you one more thing with off the topic? Why are they using testcase TC (mem_intf,input_intf,output_intf);  instead testcase TC (mem_intf,input_intf,output_intf[4]); It is so confused, I can't understand it – user5523035 Feb 22 '16 at 07:59
  • It is an array of interface. Connecting `output_intf` means all 4 instances are connected. While connecting `output_intf[4]` only connects one interface instance. Hence **port width mismatch** shall occur. You can use `output_intf[3:0]` in order to explicitly define number of instances to be connected. – sharvil111 Feb 22 '16 at 10:21
  • Thanks, is 'output_interface output_intf[4](Clock); 'and program testcase(mem_interface.MEM mem_intf,input_interface.IPinput_intf,output_interface.'OP output_intf[4]');  just meanning that only connects one interface instance? Then how to set to [0]~[3]? Where does it declare? How do we know the output_itf is 4bits? – user5523035 Feb 22 '16 at 12:14
  • `output_interface output_intf[4](Clock);` creates **4 instances**. Its an array of instances. Refer [answer to this question](http://stackoverflow.com/questions/1378159/can-we-have-an-array-of-custom-modules) for more information. – sharvil111 Feb 22 '16 at 12:20
0

To clarify named port connections (I had a surprisingly hard time finding it on google): The syntax is like this:

mygate gate0(.pin1(wire1), .pin2(wire2))

where wires can be thought of as outside of the gate and pins inside or part of the gate.

This is analogous to python named/keyword arguments: 

gate0(pin1=wire1, pin2=wire2)

However, unlike in python where arguments are passed in and the function returns a return value, in System Verilog ports may be input, output, or inout.

Further reading: http://web.engr.oregonstate.edu/~traylor/ece474/beamer_lectures/modules.pdf

qwr
  • 9,525
  • 5
  • 58
  • 102