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I'm trying to write VHDL code for a 3 input simple adder. When I type the following code, S gets the correct output value but S1 gets zero, and hence add_out also gets the wrong value.

library ieee;
use ieee.std_logic_1164.all;

entity adder is
    port( A,B : in std_logic_vector(3 downto 0);
            C : in std_logic;
    carry_out : out std_logic;
            S : out std_logic_vector(3 downto 0);
       addOut : out std_logic_vector(4 downto 0));
end adder;

architecture behavioral of adder is
signal S1 : std_logic_vector(3 downto 0);
begin
    proc : process(A,B,C) is
    variable carry : std_logic;
    begin
    carry := C;
    for i in 0 to 3 loop
    S(i) <= A(i) xor B(i) xor carry;
    S1(i) <= A(i) xor B(i) xor carry;
    carry := (A(i) and B(i)) or (B(i) and carry) or (A(i) and carry);
    end loop;
    carry_out <= carry;
    addOut <= carry & S1;
    end process proc;
end behavioral;

Why is the signal S1 not getting the same value as S?

ayerhs7
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  • You need to give more information so that someone else can try to reproduce your problem. Your for loops exist within a process; the sensitivity list will be important. Also, to answer this someone needs to do some work by creating an entity, architecture and testbench. Why not do that for them? – Matthew Taylor Mar 08 '16 at 09:59
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    Your code is still not a [Minimal, Complete, and Verifiable example](http://stackoverflow.com/help/mcve). A loop statement is a sequential statement either found in a subprogram or a process statement. Because you mentioned entity let's imagine process statements, where the one the second for loop is in is missing S1 from it's sensitivity list. Filling in all the missing pieces for your mcve and adding S1 to the sensitvity list gives [the right answer](http://i.stack.imgur.com/UgonR.png). –  Mar 08 '16 at 10:44
  • In the testbench I used A <= "1111" , B <= "1111" and C <= '0' – ayerhs7 Mar 08 '16 at 12:10
  • Please post a screenshot displaying that `S1` and `S` are not the same. – Martin Zabel Mar 08 '16 at 14:01

1 Answers1

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S1 probably (almost certainly) DOES get the same value as S.

However you wouldn't expect to see that value of S1 on addOut, thanks to the mistake in the process sensitivity list. Study the semantics of signal assignment, (aka "postponed assignment") and delta cycles, and all will become clear. (My usual explanation on this topic, if you'll excuse some self publicity)

Specifically, you have a new value on S1, but no means to wake up the process again to propagate it to any other signal.

The best fix is probably to move the addOut and carryOut assignments outside the process, where they will immediately reflect any changes on their own inputs, and reduce the likelihood of sim/synth mismatches.

Community
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