how do sequential assignments to a signal inside a process behave

Question

I'm wondering, how sequential assignments to the same signal inside of a process are treated in VHDL.

I've seen code like the following:

ENTITY some_entity IS
    ...
    ...
END some_entity;

ARCHITECTURE Behavioral OF some_entity IS
    SIGNAL some_signal : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN PROCESS (clk)
    ...
    ...
    IF condition1 THEN
        some_signal <= "01";
    ELSE
        some_signal <= (others => '0');
    END IF;

    IF condition2 THEN
        some_signal <= "10";
    ELSE
        some_signal <= (others => '0');
    END IF;

    IF condition3 THEN
        some_signal <= "11";
    ELSE
        some_signal <= (others => '0');
    END IF;
    ...
    ...
END PROCESS;
...
...
END Behavioral;

At first I thought, that this doesn't really make sense, because some_signal is assigned multiple values at the same time. Vivado is synthesizing it without complaints though and after a little research about processes, I thought it might actually behave equivalent to the following:

ENTITY some_entity IS
    ...
    ...
END some_entity;

ARCHITECTURE Behavioral OF some_entity IS
    SIGNAL some_signal : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN PROCESS (clk)
    ...
    ...
    IF condition3 THEN
        some_signal <= "11";
    ELSIF condition 2 THEN
        some_signal <= "10";
    ELSIF condition1 THEN
        some_signal <= "01";
    ELSE
        some_signal <= (others => '0');
    END IF;
    ...
    ...
END PROCESS;
...
...
END Behavioral;

Is this notion correct? And if not, what does the first code example actually do?

"last assignment wins" ... reversing the conditions as you did is correct ... however as the last `if` statement has an assignment in both arms, it overrides both earlier statements : you will never see their execution. Output will only be `"11"` or `"00"`. Key terms to understand : delta cycles, postponed assignment. — , Mar 08 '16 at 17:19
@BrianDrummond: Thanks, that's exactly what I wanted to know. I haven't thought about the last if overriding the earlier ifs, but thinking about it, it's quite obvious. Why didn't you post this comment as an answer? — FSMaxB, Mar 08 '16 at 17:22

score 3 · Accepted Answer · edited May 23 '17 at 12:23

3

"Last assignment wins" ... reversing the conditions as you did is correct ... however as the last if statement has an assignment in both arms, it overrides both earlier statements : you will never see their execution (unless it isn't executed as a result of some other condition)

Output will only be "11" or "00".

Key terms to understand : delta cycles, postponed assignment.

You might find my standard answer to similar questions useful background. It's really key to understanding what signals are for - they are how VHDL solves the problems of inter-process communication.

edited May 23 '17 at 12:23

Community

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answered Mar 08 '16 at 17:28

I actually read that "standard answer" before asking this question, but it didn't make it clear that assignments to a signal can be overwritten during one run of a process. Thanks again for this answer. – FSMaxB Mar 08 '16 at 20:04
There's a time ordered queue of scheduled values for every signal assigned in a process referred to as a *Projected Output Waveform*. It retains only one entry for any particular simulation time. An assignment scheduling a value supplants the projected value at a particular time or earlier times if present. See IEEE Std 1076-2008 10.5.2.2 Executing a simple assignment statement for an in depth description. – Mar 08 '16 at 23:26

how do sequential assignments to a signal inside a process behave

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