instancing modules verilog

Question

I have created two verilog modules which I would now like to instance in a third module. I would like the inputs of the third module to feed into the first, and then the outputs of the first to be the inputs of the second module and then finally the outputs of the second module to be the outputs of the overall module, if anyone could show an example of how I could do this in a generic manner it would be really appreciated. thanks Art

Closely related to [Verilog: How to instantiate a module](http://stackoverflow.com/q/20066850/97073). — Morgan, Mar 17 '16 at 12:11

score 0 · Accepted Answer · answered Mar 17 '16 at 11:32

It's as easy as this:

module one (input I, output O);
  assign O = I;
endmodule

module two (input I, output O);
  assign O = I;
endmodule

module top (input I, output O);

  wire W;

  one inst1 (.I(I), .O(W));
  two inst2 (.I(W), .O(O));

endmodule

http://www.edaplayground.com/x/2Mca

By default, inputs and outputs are wires. You can just connect them straight up to module inputs and outputs. You need one or more internal wires for the internal connection(s).

instancing modules verilog

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