Define 2-dimensional array of wire in verilog

Question

Here's some simple code for defining 2-dimensional array of wires in Verilog.

module test(a, b, c);

    input [63:0] a;
    input [63:0] b;
    output [63:0] c [63:0];

endmodule

When I compile the code, I get this error.

Illegal reference to net array "c".

You should take a look at http://stackoverflow.com/questions/3011510/how-to-declare-and-use-1d-and-2d-byte-arrays-in-verilog — Krouitch, Mar 21 '16 at 13:51

score 4 · Accepted Answer · edited May 23 '17 at 11:53

4

I don't think this question https://stackoverflow.com/questions/3011510/... helps with this specific problem.

You get this error, because it is illegal in Verilog (pre-2009 when it merged into SystemVerilog) to have ports that are two (or more) dimensional arrays; for arrays on ports, only simple, one-dimensional vectors are allowed.

You can have two (or more) dimensional arrays of nets or variables, as this question does explain https://stackoverflow.com/questions/3011510/....

It's worth noting that there is no such a restriction in System-Verilog (or: Multi-dimensional arrays are allowed.

edited May 23 '17 at 11:53

Community

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answered Mar 21 '16 at 15:02

Matthew Taylor

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Ok, I did not know that, my bad. Thx – Krouitch Mar 21 '16 at 15:25
4

Might be worth adding that SystemVerilog does allow this though. – Morgan Mar 21 '16 at 15:26

Serge Goncharov · Answer 2 · 2019-11-22T10:56:53.640

Although Verilog doesn't allow defining 2- or more- dimensional arrays of nets, there is a nice workaround using 'generate' statement. You can generate a set of wires then address them using a particular iteration. Here is an example:

module Example (
  input[7:0] in,
  output[7:0] out
);

  generate
    genvar i;
    for (i=0; i<=7; i=i+1) begin: stage
      wire[7:0] net;
      if (i!=0)  assign net = stage[i-1].net;
    end
  endgenerate

  assign stage[0].net = in;
  assign out = stage[7].net;
endmodule

In this example an 8*8 array of wires is created, they connected sequentially using specifier of previous iteration, after that the first and the last iterations are connected to input and output of module.

In the similar manner you can create 3 and more dimensional array.

Define 2-dimensional array of wire in verilog

2 Answers2