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I am working with a proprietary OS running on a Cortex-A5 core with MMU, caches (I&D) and branch predictor enabled. The mapping of the IO register space in the level 2 translation table is taking place after the MMU is set up and active and the caches are enabled.

The current sequence is:

  • Calculate the page table entry (PTE) value
  • Calculate the offset for the PTE in the level 2 table
  • Write the PTE into the level 2 table
  • -- Data sync barrier
  • Invalidate the data cache for the mapped page
  • Flush the branch predictor cache (which is supposedly unnecessary)

  • -- Instruction sync barrier

    This sequence doesn't seem to work with I-cache enabled. Unfortunately the debugging capabilities of the hardware are somewhat limited, but it seems that instructions performed are not the instructions that are supposed to perform for the given program counter.. Disabling the I-cache or adding the I-cache invalidation instruction after the sequence seem to work around the problem. But the reason for this is unclear to me. Why would the I-cache be affected when mapping data area? Is the sequence above correct? What would be the correct one? (And there is still a small non-negligible probability of a hardware bug).

Eugene Sh.
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  • What's the actual symptom of "doesn't seem to work"? Do you mean you get an unexpected translation fault trying to access a VA in the newly-mapped page, or something else? How about your TTBR - are the table walk attributes definitely set correctly? – Notlikethat Mar 29 '16 at 16:38
  • The actual symptom is that after getting translation fault, the dump of L2 table is showing no descriptors were written to it. As I mentioned, I don't have a conventional debug capability on the hardware but I do have the hardware signals waveforms. And they show that some instructions are just not executed or executed incorrectly (like registers are not getting the expected values and similar). Could the incorrect TTBR setting work when disabling i-cache? – Eugene Sh. Mar 29 '16 at 16:42
  • Why do you invalidate the data cache? You want to flush it (maybe you meant the I/O memory was cached!?!) It would simplify your life if the PTE memory was not cacheable. With Icache enabled things run faster meaning that the MMU/TLB are not the same as the CPU view. We can not see how you have set up memory so this is just a guess. I have [answered another question like this on SO](http://stackoverflow.com/questions/16383007/what-is-the-right-way-to-update-mmu-translation-table/16385650#16385650). – artless noise Mar 30 '16 at 05:14

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