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I am self-teaching myself VHDL, and took this answer's advice by starting with Frank Vahid's Digital Design (2nd edition).

On page 254 (link) he explains that updates to storage items occur on the next rising clock edge, therefore, at the end of a state's clock cycle. This is explained in figure 5.14 using the "Jreg" storage item, the behavior of which I understand.

What I don't understand, is why the storage item "P" behaves differently:

1) Its value is already known upon entering state S0 (whereas "Jreg" is not)

2) Upon transitioning to state S1, "P" immediately updates to the value given by state S1, whereas "Jreg" is not updated until the end of that clock cycle

Is there a difference between "Jreg" and "P" I'm not aware of? Is it an error in the example?

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Jesuis
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1 Answers1

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It appears that P is a combinational signal (not dependent on a clock) and that Jreg is sequential register (is dependent on a clock). Jreg appears to behave as a counter (which requires a clock or drive signal of some sort). The example says that the machine waits for an input signal B to go high and once it does, it sets output P high. Then, using Jreg to count the number of clock cycles passed since B went high, it holds P high until Jreg counts to a certain number of clock cycles (2) at which point both Jreg and P are reset to 0.

1) Jreg is unknown at the start and most likely so is P, however P does not have to wait for a clock tick because its a combinational signal.

2) Again Jreg is sequential so it must wait for a clock tick to change its state.

javey
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