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I write a testbench in VHDL, and there I need to reset rst signal when count_rst increases to 1000. And I can't set a value of 0 or others to count_rst. Where am I wrong?

Part of code:

signal count_rst : integer := 0;
signal rst : std_logic := '1';
signal clk : std_logic := '1';

process 
begin
clk <= '1';
if count_rst = 0 then
    rst <= '0';
else
    rst <= '1';
end if;
if count_rst > 999 then
    count_rst <= 0;
    rst <= '0';
end if;
count_rst <= count_rst + 1;
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;
end process;
levshkatov
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  • Learn the semantics of signal assignment. For example, here : http://stackoverflow.com/questions/13954193/is-process-in-vhdl-reentrant/13956532#13956532 TL/DR (applicable in any clocked process) : "last assignment wins" will explain the problem. Several easy ways to fix : left as an exercise. –  Jul 02 '16 at 13:12
  • @BrianDrummond Thanks! Is it a good solution to change signal into variable? – levshkatov Jul 02 '16 at 13:22
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    A better solution would be to learn how signals work so you can use either. –  Jul 03 '16 at 09:53

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