1

I want to emulate various multi-core hardware with Risc V and Spike but I am really struggling to find documentation: for instance I don't even know where a typcial RISC-V processor begins execution on reset and cannot seem to find this information in the ISA documentation.

Is the answer to look at the Spike sources? Or is there some other pool of documentation I have missed?

adrianmcmenamin
  • 1,081
  • 1
  • 15
  • 44

2 Answers2

2

What you are asking about is not a part of the user-level ISA, but rather, the Platform Specification.

Unfortunately, such a manual does not yet exist.

Your best bet, particularly as the platform and privileged-level specifications are still under rapid development, is to look at the Spike source code, as it is the "Golden Model".

To answer your question about the boot PC, just see what Spike does:

spike -d hello.riscv
Chris
  • 3,827
  • 22
  • 30
0

Regarding bootstrap PC after reset, according to post linked below it is from 0x200.

How can I compile C code to get a bare-metal skeleton of a minimal RISC-V assembly program?

  • I am still trying to figure out how to get the example in linked post to work on up-to-date rocket.
Community
  • 1
  • 1
krembo
  • 25
  • 6