In the end what I want to do is to use a streaming interface with single precision floating point arrays in Vivado Design Suite to build hardware accelerators. HLS User Guide UG902 shows that is possible to create HW accelerators (starting from C, C++, SystemC, OpenCL code) using different interfaces.
If you want to use an AXI4 streaming interface, HLS synthesizes the signals TREADY and TVALID but it doesn't synthesize the signal TLAST necessary to connect the RTL interface generated to Zynq Processing System (ARM9 cores in my case). In order to solve this problem, Xilinx gives you the possibility to use this library
#include "ap_axi_sdata.h"
Inside there is the struct - template:
#include "ap_int.h"
template<int D,int U,int TI,int TD>
struct ap_axis{
ap_int<D> data;
ap_uint<D/8> keep;
ap_uint<D/8> strb;
ap_uint<U> user;
ap_uint<1> last;
ap_uint<TI> id;
ap_uint<TD> dest;
};
I have two problems:
- If I want to use only TLAST and not the others, I try to set up U, TI and TD to zero but I get an error.
- If I want to use 'float' and not 'ap_int' and I try to change it inside the template I get another error.
How can I handle and manage streaming interface in HLS with floating point data without encountering these two problems?