Concatenation of Array at Output Verilog

Question

Total noob here, just to be clear. Only about a month in to learning Verilog.

So I have some user-defined parameters, and I want to put out a concatenation of all items in an array. For instance, if the array length were static (in this case, an array of 10 12-bit items), I could certainly do something like:

    reg [11:0] array [9:0];
    output <= {array[9],...,array[0]};

But what if the array length is user-defined and therefore not a static value? For instance, if I wanted two outputs like so, with length being a parameter:

    output1 <= array[0];
    output2 <= {array[length-1],...,array[1]};

Been banging my head against this for a minute or two and haven't found anything in my internet searches... Hope I'm being clear enough...

wilcroft · Accepted Answer · 2016-08-09T16:26:43.920

0

Let's say you have the following:

parameter NUM_ITEMS = 10;
parameter LOWER = 1;
parameter UPPER = 9;
reg [11:0] array [NUM_ITEMS-1:0];
reg [12*(NUM_ITEMS-1)-1:0] output;

The following could work:

integer i;
always@(*) begin
    for (i=0; i <= UPPER; i=i+1)
        output[i*12+:12] = array[LOWER+i];
        //alternatively output [12*i+11:12*i] = array[LOWER+i];
end

Your array elements would need to be sequential, though.

edited Aug 09 '16 at 16:26

answered Aug 09 '16 at 16:10

wilcroft

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Yes, I thought so, but I get a compiler error saying "cannot assign an unpacked type to a packed type". I guess I'm not yet clear on the difference or the syntax. – Bobby Aug 09 '16 at 16:22
Sorry about that - mistook the "nooby-ness" involved. I've re-written my answer based on your edits. – wilcroft Aug 09 '16 at 16:27
No worries, that worked. All I have to do now is read up to fully understand bit slicing. – Bobby Aug 09 '16 at 17:37

score 0 · Answer 2 · edited May 23 '17 at 12:08

you could try assigning the array in a loop to the variable output2. You will move across the bits of the output2 variable and assign the value from each element of array into output2. WIDTH_ARRAY is the width of array and has to be a constant.

parameter SZ = 10;
parameter WIDTH_ARRAY = 8;

reg [WIDTH_ARRAY-1:0] a[SZ] = {1,1,1,1,1,1,1,1,1,1}  ;
reg [SZ*WIDTH_ARRAY:0] output2;

output1 <= array[0];
for ( int i = 0 ; i<SZ-1;i++)
   begin
        output2[(i*WIDTH_ARRAY)+:WIDTH_ARRAY] = array[i+1];
   end

You cannot assign array to output2 directly as one is unpacked and other is a packed structure .

+: is called the bit slice operator. Indexing vectors and arrays with +:

Concatenation of Array at Output Verilog

2 Answers2