How can I generate FIRRTL from chisel code?

Question

How can I generate FIRRTL file from chisel code? I have installed sbt, firrtl and verilator according to the github wiki. And created a chisel code for simple adder. I want to generate the FIRRTL and covert it to Verilog? My problem is how to get the firrtl file from the chisel code. Thanks.

Source file : MyQueueTest/src/main/scala/example/MyQueueDriver.scala

package example

import chisel3._
import chisel3.util._

class MyQueue extends Module {
  val io = IO(new Bundle {
    val a = Flipped(Decoupled(UInt(32.W)))
    val b = Flipped(Decoupled(UInt(32.W)))
    val z = Decoupled(UInt(32.W))
  })  

  val qa = Queue(io.a)
  val qb = Queue(io.b)

  qa.nodeq()
  qb.nodeq()

  when (qa.valid && qb.valid && io.z.ready) {
    io.z.enq(qa.deq() + qb.deq())
  }
}

object MyQueueDriver extends App {
  chisel3.Driver.execute(args, () => new MyQueue)
}

score 3 · Accepted Answer · edited May 23 '17 at 12:32

3

I asked a similar question here. The solution could be to use full template provided here, or you can simply do that:

Add these lines at the end of your scala sources :

object YourModuleDriver extends App {
  chisel3.Driver.execute(args, () => new YourModule)
}

Replacing "YourModule" by the name of your module.

And add a build.sbt file in the same directory of your sources with these lines :

scalaVersion := "2.11.8"

resolvers ++= Seq(
  Resolver.sonatypeRepo("snapshots"),
  Resolver.sonatypeRepo("releases")
)

libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "3.0-SNAPSHOT"

To generate FIRRTL and Verilog you will just have to do :

$ sbt "run-main YourModuleDriver"

And the FIRRTL (yourmodule.fir) /Verilog (yourmodule.v) sources will be in generated directory.

edited May 23 '17 at 12:32

Community

1
1

answered Nov 29 '16 at 07:42

FabienM

3,421
23
45

Thanks a lot, I was able to see the Verilog file. When I have `package ` in my source code `$ sbt "run-main YourModuleDriver"` didnt work. It gave Class Not Found exception. – Aditha Rajakaruna Dec 03 '16 at 05:57
What is the name of your module ? Can you post sources ? – FabienM Dec 03 '16 at 14:34
I apologize for the long delay in response. I added the source code to the question. When I removed the `package` in the source code and move the source code to dir MyQueueTest/src/main/scala/ it works like a charm. – Aditha Rajakaruna Dec 29 '16 at 06:37
Please, don't forget to mark question has "solved" then. – FabienM Jan 02 '17 at 15:47

How can I generate FIRRTL from chisel code?

1 Answers1