vhdl how make signal choice on structual code

Question

I want make menu choice

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;


ENTITY aluall IS
PORT(
        A:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
        B:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
        CLK:IN STD_LOGIC;
        LOAD: in std_logic;
        RESET: IN STD_LOGIC;
        D:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
        END aluall;

ARCHITECTURE structual OF aluall IS
SIGNAL finor,Rsub2,Rsub,Radd,Radd2,Radd1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL rAnd : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal rePiso : std_logic;
SIGNAL fmulti : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL compare: STD_LOGIC_VECTOR(1 DOWNTO 0);
signal repo: std_logic_vector(7 downto 0);
signal choice: integer range 0 to 10;


COMPONENT orGate
PORT(    A:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
         B:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
         F:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
        END COMPONENT;


COMPONENT   andGate
PORT(    A:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
         B:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
         F:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
        END COMPONENT;

COMPONENT add1
PORT(
  A : in std_logic_vector(7 downto 0);
  C : out std_logic_vector(7 downto 0));
END COMPONENT;

COMPONENT add2

port(
  B : in std_logic_vector(7 downto 0);
  C : out std_logic_vector(7 downto 0));

END COMPONENT;



COMPONENT add

port(
  A : in std_logic_vector(7 downto 0);
  B : in std_logic_vector(7 downto 0);
  C : out std_logic_vector(7 downto 0)); 
END COMPONENT;



BEGIN --i want make choice menu for what go to output
 process(A,B,choice)
 begin
 if(choice = 0) then
label0: andGate PORT MAP (A,B,rAnd);
else
label1: orGate PORT MAP (A,B,finor);
end if;
label2: add PORT MAP (A,B,Radd);
label3: sub PORT MAP (A,B,Rsub);
label4: sub2 PORT MAP (A,B,Rsub2);



end structual;

I have error Illegal sequential statement.

Format the code properly and give the full error message including the line number it refers to. — , Nov 30 '16 at 17:33
And now I can see : you can't instantiate components in a process. So you need to learn the difference between sequential and concurrent statements, and how to do what you want (a) either with sequential statements or (b) in the concurrent statement region. BUT NOTE : You cannot make gates appear and disappear at runtime. So you probably need both gates to exist permanently, and choose between their outputs. — , Nov 30 '16 at 17:38

score -1 · Answer 1 · answered Nov 30 '16 at 23:38

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;

ENTITY aluall IS
PORT(
        A:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
        B:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
        code : std_logic_vector(3 downto 0);
        CLK:IN STD_LOGIC;
        D:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
        END aluall;

ARCHITECTURE structual OF aluall IS
SIGNAL finor,Rsub2,Rsub,Radd,Radd2,Radd1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL rAnd : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal rePiso : std_logic;
SIGNAL fmulti : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL compare: STD_LOGIC_VECTOR(7 DOWNTO 0);
signal repo: std_logic_vector(7 downto 0);


COMPONENT orGate
PORT(    A:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
         B:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
         F:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
        END COMPONENT;


COMPONENT   andGate
PORT(    A:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
         B:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
         F:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
        END COMPONENT;

COMPONENT add1
PORT(
  A : in std_logic_vector(7 downto 0);
  C : out std_logic_vector(7 downto 0));
END COMPONENT;

COMPONENT add2

port(
  B : in std_logic_vector(7 downto 0);
  C : out std_logic_vector(7 downto 0));

END COMPONENT;

COMPONENT multi
 port(
  A : in std_logic_vector(7 downto 0);
  B : in std_logic_vector(7 downto 0);
  C : out std_logic_vector(15 downto 0));

END COMPONENT;

COMPONENT add

port(
  A : in std_logic_vector(7 downto 0);
  B : in std_logic_vector(7 downto 0);
  C : out std_logic_vector(7 downto 0)); 
END COMPONENT;

COMPONENT sub
port(
  A : in std_logic_vector(7 downto 0);
  B : in std_logic_vector(7 downto 0);
  C : out std_logic_vector(7 downto 0));  

END COMPONENT;

COMPONENT sub2

port(
  A : in std_logic_vector(7 downto 0);
  B : in std_logic_vector(7 downto 0);
  C : out std_logic_vector(7 downto 0)); 

 END COMPONENT;

COMPONENT comparing
port(
  A : in std_logic_vector(7 downto 0);
  B : in std_logic_vector(7 downto 0);
  C : out std_logic_vector(7 downto 0)
 );
END COMPONENT;

COMPONENT piso
port(
CLK,LOAD : in std_logic;
PI : in std_logic_vector(7 downto 0);
SO : out std_logic
);
END COMPONENT;


COMPONENT pipo

port(
clk:in std_logic;
pi: in std_logic_vector(7 downto 0);
po:out std_logic_vector(7 downto 0)

);
end COMPONENT;



begin
label0: andGate PORT MAP (A,B,rAnd);
label1: orGate PORT MAP (A,B,finor);
label2: add PORT MAP (A,B,Radd);
label3: sub PORT MAP (A,B,Rsub);
label4: sub2 PORT MAP (A,B,Rsub2);
label5: add1 PORT MAP (A,Radd1);
label6: add2 PORT MAP (B,Radd2);
label7: multi PORT MAP (A,B,fmulti);
label8: comparing PORT MAP (A,B,compare);
process(A,B,CLK,code)
begin




if (code = "0000") then
D<= rAnd;
elsif(code ="0001") then
D<= finor;
elsif(code ="0010") then
D<=Rsub;
elsif(code = "0011") then
D<=Radd;
elsif(code = "0100") then
D<=Rsub;
elsif(code = "0101") then
D<=Rsub2;
elsif(code = "0110") then
D<=Radd1;
elsif(code = "0111") then
D<=Radd2;
elsif(code = "1000") then
D<=fmulti;
else
D<=compare;
end if;
end process;



end structual;

i run this code and always run first if and last...why?

enter image description here

This appears to be a new question, not an answer to the previous one. This isn't a chat room. You need to post this as a new question. — Matthew Taylor, Dec 01 '16 at 08:55
However, you appear to think you are writing software. You are not. VHDL is a _Hardware_ Description Language. Hardware doesn't get 'run', it exists for all time. andGate, orGate etc are hardware sub-blocks. From you trace, it looks like there is no logic behind your sub-blocks. (Think of a component as being like an IC socket. Think of an entity as being like an IC that plugs into it.) My guess is that you have many components with no entities bound to them. ie You have many sockets with no ICs in them. This is why you have lots of `'U'`s. — Matthew Taylor, Dec 01 '16 at 08:56
Why are you using _component instantiation_ anyway? _Direct instantiation_ is easier and more suited to this design. [http://electronics.stackexchange.com/questions/16692/vhdl-component-vs-entity](http://electronics.stackexchange.com/questions/16692/vhdl-component-vs-entity) — Matthew Taylor, Dec 01 '16 at 08:59
This is along the right lines to solve the original problem. But it appears you have a HUGE amount to learn - not so much about VHDL, but about hardware. Without your testbench, nobody can help much, but at a guess you're running into signal timing problems such as race conditions. VHDL has the best way of modelling these, with the delta cycle. Start here. http://stackoverflow.com/questions/13954193/is-process-in-vhdl-reentrant/13956532#13956532 My recommendation would be to make that process a synchronous (clocked) process. — , Dec 01 '16 at 10:38

vhdl how make signal choice on structual code

1 Answers1