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In modern Intel architectures where QPI replaces FSB, the RAM memory interfaces directly to the CPU. If this is a fact, why do chipsets designed for such architectures have RAM memory interface specifications? Shouldn't only the CPU be connected to RAM? As an example, see H81 Chipset.

PDuarte
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  • Can you link to a URL for your example? I've wondered this, too, but it would be a better question if we had a specific example of *what* the chipset docs say about memory. (e.g. is it just total memory supported, leaving the speed specs to the CPU's memory controller?) – Peter Cordes Dec 17 '16 at 21:15
  • I wouldn't be surprised if there are market-segmentation artificial reasons here. e.g. the cheap chipsets tell the CPU not to support 2 DIMMs per channel. Or maybe Intel just won't license the chipsets to mobo makers unless they restrict the cheapest chipsets to 2 DIMMs total instead of 4 DIMMs. – Peter Cordes Dec 17 '16 at 21:16

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