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Questions tagged [nehalem]

Nehalem is the codename for an Intel processor microarchitecture, successor to the Core microarchitecture. Nehalem processors use the 45 nm process.

See more on https://en.wikipedia.org/wiki/Nehalem_(microarchitecture)

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floating point operations per cycle - intel

I have been looking for quite a while and cannot seem to find an official/conclusive figure quoting the number of single precision floating point operations/clock cycle that an Intel Xeon quadcore can complete. I have an Intel Xeon quadcore E5530…
user3495341
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Software prefetching across page boundary on x86

My understanding is that hardware prefetching will never cross page boundaries. I'm wondering if a software prefetch has the same restriction i.e. can I use a software prefetch to avoid a future TLB miss. From searching around, it appears to be…
jmetcalfe
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What is the maximum possible IPC can be achieved by Intel Nehalem Microarchitecture?

Is there an estimation for the maximum Instructions Per Cycle achievable by the Intel Nehalem Architecture? Also, what is the bottleneck that effects the maximum Instructions Per Cycle?
user3842413
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Memory access by multiple threads

I'm writing a multi threading java application that runs on Nehalem processor. However I have a problem that starting from 4 threads I almost don't see the speedup in my application. I've made some simple test. I've created a thread that just…
jutky
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Unexpectedly large number of TLB misses in simple PAPI profiling on x86

I am using the PAPI high level API to check TLB misses in a simple program looping through an array, but seeing larger numbers than expected. In other simple test cases, the results seem quite reasonable, which leads me to think the results are real…
jmetcalfe
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Nehalem Xeon performance on 32-bit OS, XP vs 2003

I have to run 32-bit code on WinXP or Win2003. Nehalem Xeons (5500 series) should be the fastest, but I'm not sure what'll happen with the memory arrangement. I'm unsure about 2 parts: To get a maximal speed memory setup, I'll need to install at…
ggruschow
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Minimizing inter-core Communication in a NUMA architecture

Can anyone highlight ways by which inter-core communication can be reduced in a NUMA multicore architecture. Case study Intel NEHALEM micro architecture.
Oyinlade Olumide
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Number of banks in Nehalem l2 cache

I was just studying the access time for different cache configurations when i stumbled on a term in the cacti interface "Number of Banks". Number of banks is the number of interleaved modules in a cache which increases the bandwidth of the cache…
prathmesh.kallurkar
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I need an flp file for the Intel Xeon X5550 gainestown for HotSpot

I simulated its default profile, gainestown, with the sniper simulator, and now, I want to feed the data into HotSpot to calculate the heat, so I need a floor plan file (.flp) for gainestown.
JunYH
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Nehalem Architecture

Can anyone tell me how many registers are in the core i7 with the nehalem architecture? And explain a little to me the registers work in this architecture? I found only MOB register functionalities, nothing more.
Luís Felipe
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Nehalem memory architecture address mapping

Given a 2 processor Nehalem Xeon server with 12GB of RAM (6x2GB), how are memory addresses mapped onto the physical memory modules? I would imagine that on a single processor Nehalem with 3 identical memory modules, the address space would be…
ptman
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Why do Intel QPI chipsets have memory specifications?

In modern Intel architectures where QPI replaces FSB, the RAM memory interfaces directly to the CPU. If this is a fact, why do chipsets designed for such architectures have RAM memory interface specifications? Shouldn't only the CPU be connected to…
PDuarte
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Mapping of memory addresses to physical modules in Windows XP

I plan to run 32-bit Windows XP on a workstation with dual processors, based on Intel's Nehalem microarchitecture, and triple channel RAM. Even though XP is limited to 4 GB of RAM, my understanding is that it will function with more than 4 GB…
Josef Grahn
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