When exactly to use logic data type and when bit data type in system verilog?

Question

I know that logic is a 4-state and bit is 2 state, using bit will make to lose testing of x and z. But when exactly bit and when logic?

Possible duplicate of [Difference of SystemVerilog data types (reg, logic, bits)](http://stackoverflow.com/questions/13282066/difference-of-systemverilog-data-types-reg-logic-bits) — Rcordoval, Dec 28 '16 at 04:37

score 0 · Answer 1 · answered Dec 28 '16 at 20:01

0

This paper should cover your questions:

TLDR; bit is better for performance (only 2 states to model), but hides X-propagation issues.

answered Dec 28 '16 at 20:01

Arun D'souza

1 Answers1