Even though the internal architecture of the CPU might be harvard-like, with separate instruction and data caches and buses, the rest of the SoC still only has got one main memory, and both instruction and data buses connect to the same memory. From https://en.wikipedia.org/wiki/ARM9:
With this design generation, ARM moved from a von Neumann architecture (Princeton architecture) to a Harvard architecture with separate instruction and data buses (and caches), significantly increasing its potential speed. Most silicon chips integrating these cores will package them as modified Harvard architecture chips, combining the two address buses on the other side of separated CPU caches and tightly coupled memories.
From the linked page about modified Harvard architecture:
Most modern computers instead implement a modified Harvard architecture.
The most common modification builds a memory hierarchy with a CPU cache separating instructions and data. This unifies all except small portions of the data and instruction address spaces, providing the von Neumann model. Most programmers never need to be aware of the fact that the processor core implements a (modified) Harvard architecture, although they benefit from its speed advantages. Only programmers who write instructions into data memory need to be aware of issues such as cache coherency.
The same also goes for any modern x86 chip.
This doesn't pose any issue for Raspbian, which is just a special recompile of normal Debian for Raspberry Pis; the main difference in raspbian is that it has got a different arm target (armv6+vfp hardfloat) than the other existing arm debian distributions (which target either armv4t or armv7+vfp hardfloat).
