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MIPS ISA has an R type instruction, and the R instruction has an opcode field at its first 6 bits and a funct field at its last 6 bits. So why are the ISA designed like this? How about combine them into a 12-bits field?

NAND
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Daidamai
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    why should you combine them into 12-bits? –  Feb 22 '17 at 14:26
  • Because all instructions must decode starting from a common point. A 12 bit opcode would chew too many bits for other non-R types which use them for other things. (e.g.) the `j` and `jal` instructions use the remaining bits to specify the address (i.e. no funct field). After decoding the opcode, each instruction is free to interpret the remaining 26 bits in _any_ way. immediate insts (e.g. `ori`) use the last 6 as part of the 16 bit immediate operand – Craig Estey Feb 22 '17 at 18:25

2 Answers2

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MIPS instruction format

My idea is that the three kinds of instructions share a prefix of 6-bit opcode. And for R and I types, the next 5 bits decide source register. If we combine opcode and funct for R instruction, the instruction format is not so consistent between R and I, which may make processor's design complex.

Community
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gcc17
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  • I guess you could put `funct` right next to `opcode`, and move the other fields. But that would require splitting up the immediate for I-type. RISC-V does split up immediates for some instruction formats, and the RISC-V manual explains some of the design motivations to reduce muxing necessary for decode, and to simplify software sign-extension via arithmetic right shift by putting the top bit of the immediate at the far left of the instruction. [Why are RISC-V S-B and U-J instruction types encoded in this way?](https://stackoverflow.com/q/58414772) – Peter Cordes Jan 25 '21 at 17:23
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How about if combine them in 12-bits filed?

Since the opcode is the same for some operation in MIPS and if you change the funct than you can't differentiate which operation the instruction does, for example consider the following add(R,0,32) add has opcode 0 and funct 32
And also consider that and(R,0,36) and has also opcode 0 but different funct in this case 36 which means it's and AND operation.

check the MIPS Reference Sheet.