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According to my understanding, load/store operations would access some data of a virtual memory address(vaddr), and this vaddr would be translated into physical address(paddr) in order to be fulfilled by the memory hierarchy. The translation process would first look up in TLB, if no match is found, a multi level(?) page table look up is then triggered.

My question is: will the page table be put in L1D cache, L2 cache or LLC, besides the quite limited TLB entries?

yjshen
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    This is implementation specific, but usually done on many CPUs, either on the normal caches or on dedicated ones. See for example - http://stackoverflow.com/questions/26945448/what-is-pde-cache/26945867 – Leeor May 18 '17 at 17:34
  • PTE - the single translation element of page table - with specific translation from this virtual page to some physical page will be stored in TLB buffer (as TLB entry) for faster access (ld/st needs phys addr to find data in caches or memory). Data from the page will be partially cached in data cache (LLC/L2/L1D), but single load/store operation does not load full page into cache. If your program does linear operations on the all data of the page, data from the page will probably be prefetched by some hardware prefetchers to some cache. – osgx May 20 '17 at 03:49
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    Does this answer your question? [What happens after a L2 TLB miss?](https://stackoverflow.com/questions/32256250/what-happens-after-a-l2-tlb-miss) – Peter Cordes Mar 12 '21 at 09:34

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