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Recently I've spent a lot of time thinking about hardware emulation and virtual machines. I've been trying to design a vm thats based on NES hardware. However, I can't seem to find any information on how the NES accessed more than 256 bytes of RAM. According to the NES wiki, the machine had 2k of CPU RAM. As the NES is an 8 bit machine addresses can only go up to 255. So how was this possible? Did they simply store larger addresses in multiple registers or something?

Thanks for your time.

xXxK3vin_Spac3yxXx
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  • https://wiki.nesdev.com/w/index.php/Nesdev_Wiki – xxbbcc Jun 13 '17 at 15:35
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    cross-site duplicate: [How can 8-bit processor support more than 256 bytes of RAM?](https://electronics.stackexchange.com/q/57950/27052) – phuclv Jun 13 '17 at 15:44
  • I would say obviously they were not limited to 256 bytes, simple wikipedia searches should show that. Various specific solutions can and have happened, x86 used segments (was 16 bit not 8 but same problem), others in the cpu added additional address bits that were accessed in some way and fed into the over all address, space, could also solve the problem off cpu where you have logic that supplies the additional address bits and you can change those with software. – old_timer Jun 13 '17 at 19:07
  • Although on-topic here, you are likely to get a better reception asking "conceptual" retrocomputing questions like this one over on [Retrocomputing.SE]. Please be sure to read their FAQ and How To Ask page before posting there, though! – Cody Gray - on strike Jun 14 '17 at 05:50

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The NES has a 6502 family CPU built by Ricoh (it's missing the BCD mode). 6502 CPUs have a 16 bit address space which can be addressed using various modes.

You can directly specify a 16 bit address in the instruction i.e.

LDA $8000 will load the accumulator with the data at address $8000

LDA $8000,X will add the X register to $8000 then read the value at that address (i.e. if X is 76 then address $8076)

More interesting is the Zero page which can be viewed as 128 16 bit pointer registers. Zero page instructions only need one byte to specify the address (but need more cycles to perform the indirection)

So if the memory at $0004 contains the value $1234 and the Y register is $21 then the instruction

LDA ($04),Y will read the $1234 from the zero page then add the Y register to get the address $1255, the contents of $1255 is then loaded into the accumulator. There are more addressing modes but that feels more like something for a tutorial on 6502 assembly.

Broadly speaking processors are classed by the width of their data path, however CPU designers might specify less data or address pins on the physical chip for cost reasons.

For example the 8088 & 8086 were classed as 16 bit devices with a 20 bit address bus and either an 8 or 16 bit data bus. The Motorola 68000 had another pin reduced version with a 8 bit bus (68008 used in the Sinclair QL) and later parts had full 32 bit address / data buses.

PeterI
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Yes, using "multiple registers" is referred as bank switching, either in the machine's hardware or on the cartridges: https://en.wikipedia.org/wiki/Bank_switching

Josep Valls
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