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I wrote this code in NASM:

PADDD mm0, mm1

And it was assembled with no errors, but this instruction, though it exists in NASM, I couldn't find it in Intel Instructions Manuals, all I found is this: 

PADDD xmm1, xmm2/m128

Which takes an xmm register and not an mm register.
This is the opcode of PADDD mm0, mm1: 0FFEC1
And this is the opcode of PADDD xmm0, xmm1: 660FFEC1
So why PADDD mm0, mm1 is missing in Intel's Instructions manuals?

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  • I don't know your source, but it exists [here](http://x86.renejeschke.de/html/file_module_x86_id_226.html). – Ben Steffan Jun 18 '17 at 16:18
  • @BenSteffan I found it here too : https://en.wikipedia.org/wiki/X86_instruction_listings. But in the manual, it doesn't exist. – Bite Bytes Jun 18 '17 at 16:22
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    You seem to be correct. In the latest [Intel manual](https://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developer-vol-2b-manual.html) the mmx variant is notably absent. In an older version of the [Intel manual from 2005](http://www.scs.stanford.edu/05au-cs240c/lab/ia32/IA32-2B.pdf) it is listed. – Michael Petch Jun 18 '17 at 16:40
  • For the record, it's also present in the march 2017 volume 2. – Jester Jun 18 '17 at 18:06

1 Answers1

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This is a simple case of a typo/omission in the current version of Intel's manuals.

On this site, which hosts a copy of the Intel docs (although not necessary the latest Intel docs), the opcode for MMX is present:

Opcode/Instruction    Op/En                64/32 bit Mode Support     CPUID Feature Flag  Description
0F FC /r1            PADDB mm, mm/m64 RM  V/V                        MMX                 Add packed byte integers from mm/m64 and mm.

You will also find it in an older Intel manual from 2005, as well as in the March 2017 version.

Nothing to see here; please move along.

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