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I know yosys has limited tri-state support, but I'm looking for a possible workaround. The following circuit:

module TBUF2
(
inout SALIDA1,
inout SALIDA2,
input OE,
output C);

assign SALIDA1=OE ? 1'b0 : 1'bZ;
assign SALIDA2=OE ? 1'b0 : 1'bZ;

wire e;
assign e=SALIDA1 & SALIDA2;
assign C=e;
endmodule

Is interpreted as:

TBUF2 parsed tree

Note that when OE is 0 C=SALIDA1 and SALIDA2. During the opt pass, the opt_merge pass removes $2 mux and generates:

TBUF2 optimized

This breaks the circuit (when OE is 0 then C=SALIDA1). I realize this is because yosys/ABC doesn't really understand the consequences of the "1'z" input. Is it possible to keep muxes that meet the following criteria?:

1) At least one input is 1'Z

2) Its output drives an inout pin

Here is the script to reproduce it:

read_verilog tbuf2.v
proc
show -format dot -prefix tbuf2_01
opt
show -format dot -prefix tbuf2_02
Salvador E. Tropea
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  • I don't understand in what way opt_merge breaks the circuit here in your oppinion. The drivers for SALIDA1 and SALIDA2 are identical! Merging them seems to be a perfectly valid transformation. Using e.g. two different enable signals OE1 and OE2 will prevent opt_merge from merging the two drivers. Also: If you want anyone to be able to reproduce what you are doing you also have to post your Yosys scripts. And finally: I think you misunderstand what the "BUF" is in the show output. Simply running "opt_clean" should get rid of the BUFs for SALIDA1 and SALIDA2 in your first example. – CliffordVienna Jun 30 '17 at 14:39
  • Thanks Clifford, but this is not valid. When OE is 0 both muxes ($1 and $2) have its output with 1'Z. In this situation the outside world controls what SALIDA1 and SALIDA2 are, and the output C is the AND (SALIDA1 AND SALIDA2). In the optimized circuit C==SALIDA1. I understand this is part of the "limited support", but isn't valid. I'll edit the original post to remove the BUFs stuff and propose a solution. – Salvador E. Tropea Jun 30 '17 at 15:21
  • As I've said before, you seem to misunderstand what BUF means in the "show" output. The output world still controls SALIDA1 and SALIDA2 in the optimized version. – CliffordVienna Jun 30 '17 at 15:24
  • Please read all my comment. I also added it to the question. The circuit is wrong. When OE=0 the original circuit is an AND between SALIDA1 and SALIDA2. In the optimized version is a copy of SALIDA1. Both SALIDA1 and SALIDA2 are connected to the outside world. If the design says those pins are inout the synthesis tool must take extra care because the outside world will also drive those pins. – Salvador E. Tropea Jun 30 '17 at 15:30
  • I see. Thanks for posting the scripts. Call "tribuf" after running "proc" and updated to git commit 18c030a. – CliffordVienna Jun 30 '17 at 15:45
  • Thanks! I compiled the last git version and used the tribuf command, now I'll try with the real world design. – Salvador E. Tropea Jun 30 '17 at 16:13

1 Answers1

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Convert the tristate buffer $mux cells to $tribuf cells by running the tribuf command after proc and before running any opt commands.

CliffordVienna
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