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I am getting an error to compile code line 9, so I am not sure how to dynamically access arrays. I have to build logic [255:0] from the received bytes. (Looks like I have to review data types of SystemVerilog :( ). Thanks in advance.

module test;

    task test_array (logic [7:0] B);
      static logic [255:0] l_ar_B;

      l_ar_B[7:0] = B;

      for(int i=0; i<32; i++)
        l_ar_B[(i*8+7) : (i*8)] = B; // Error-[IRIPS] Illegal range in part select
      $stop();

    endtask

    initial begin
      $display("Start");
      test_array(8'h11);
    end

endmodule
tk421
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albert waissman
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1 Answers1

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When using the range selection with [M : N] syntax, M and N must be be constants. You should use part-select addressing with the syntax [s +: W], where W is a constant for the width and s can be a variable indicating the starting bit position. The +: been around since IEEE Std 1364-2001 (Verilog 2001). See Indexing vectors and arrays with +:

for(int i=0; i<32; i++)
  l_ar_B[(i*8) +: 8] = B;

Since you are doing replication, you can use l_ar_B = {32{B}}; to get the same result in a singe step.

Greg
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  • Thanks. Very useful, did not found any where. – albert waissman Jul 03 '17 at 18:13
  • @albertwaissman , on this site "thanks" is best give by up-voting and ckecking the accept answer icon (if the answer satisfies your question and is the best answer). This helps others know you are not looking for more answers and helps those that have the same question as you. – Greg Jul 06 '17 at 15:55