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I have been reading on memory management, protection, paging etc. and while I do get the gist of virtual memory, there is two things I'm still a bit fuzzy about.

Now when a user space process gets started, kernel setups the memory and paging table for it (as I understand it). Now after the program is started, how exactly does the memory access work? Does every single action that needs to read/write memory (so basically pretty much everything) need to go through the kernel for address translation, or can the process "directly" access the memory. Meaning is there a component (mainly mmu) that does the translation on-the-fly without any need to switch to kernel. for the translation.

tl;dr is there a physical component that does virtual-> physical address mapping, or is all of this handled by kernel.

p.s. if it does matter I'm talking about x86 cpu and linux.

jfp
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  • The kernel provides for the necessary paging structures and sets the system up for paging but the address translation itself is done purely in hardware, except for a page fault, possibly. Read the suggested duplicate post or [this Intel manual](https://software.intel.com/sites/default/files/managed/a4/60/325384-sdm-vol-3abcd.pdf), esp. chapter 4. – cadaniluk Aug 19 '17 at 19:43
  • The MMU handles this without invoking the kernel, yes. If it's something the MMU can't handle (such as a page still on disk), it's just register as nonexistant. Any access to such a page causes the MMU to register a page faults, which is then handled by the kernel – that other guy Aug 19 '17 at 22:00
  • Each core has hardware that can read page tables, and cache these translations. It's called a TLB (translation lookaside buffer), and is what allows modern CPUs like Intel Haswell to sustain a throughput of 2 loads + 1 store per clock cycle. (And there's a separate iTLB for instruction-fetch). On x86, [TLB misses are resolved by page-walk hardware](https://stackoverflow.com/questions/32256250/what-happens-after-a-l2-tlb-miss/32258855#32258855) that reads the page tables without kernel intervention. (And it can even do this speculatively, as a sort of TLB prefetch.) – Peter Cordes Aug 20 '17 at 14:43
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    @thatotherguy: You could call the TLBs + page-walk hardware "the MMU" if you wanted to, but really paging support is baked in to various parts of the core, including the L1 caches (which are virtually indexed/physically tagged, although it's done in such a way that they're also physically indexed, using only address bits below the page split). Intel uop caches are virtually addressed, so iTLB invalidations have to evict uop cache lines. There really isn't a separate thing you could call "the MMU", but it does work as a simple mental model. – Peter Cordes Aug 20 '17 at 14:48

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