0

I have to implement a 30" counter in my state machine, so if in some state it reaches 30" it return to the initial state (Espera). I think I have to do a frequency divider because then i have to implement the code in my 50mHz FPGA. Even so, I have the problem that I do not know how to implement that frequency divider in each state. Any idea how to do it? Here is my code:

LIBRARY ieee;
USE ieee.std_logic_1164.all;`

ENTITY moore IS PORT(
   clk: IN std_logic;
   m_5: IN std_logic; m_10: IN std_logic; m_20: IN std_logic;
   reset_maquina: IN std_logic;
   seleccionar_producto: IN std_logic;
   gorro: OUT std_logic; insignia: OUT std_logic;

END moore;

ARCHITECTURE maquina_exp OF moore IS
   TYPE estado IS (espera, t_5, t_10, t_15, t_20, t_25, t_5_aux, t_10_aux, 
   t_15_aux, t_20_aux, t_25_aux);
SIGNAL cuenta: estado;

BEGIN    

   PROCESS (clk, reset_maquina)     
   BEGIN
       IF reset_maquina = '1' THEN cuenta <= espera;

       ELSIF (clk'EVENT AND clk='1') THEN

        CASE cuenta IS
            WHEN espera =>
                IF m_5 = '1' THEN cuenta <= t_5_aux;
                ELSIF m_10 = '1' THEN cuenta <= t_10_aux;
                ELSIF m_20 = '1' THEN cuenta <= t_20_aux;
                END IF;
                insignia <= '0';
                gorro <= '0';


            WHEN t_5 =>
                IF m_5 = '1' THEN cuenta <= t_10_aux;
                ELSIF m_10 = '1' THEN cuenta <= t_15_aux;
                ELSIF m_20 = '1' THEN cuenta <= t_25_aux;
                END IF;

            WHEN t_10 =>
                IF m_5 = '1' THEN cuenta <= t_15_aux;
                ELSIF m_10 = '1' THEN cuenta <= t_20_aux;
                ELSIF m_20 = '1' THEN cuenta <= t_25_aux;
                END IF;

            WHEN t_15 =>
                IF m_5 = '1' THEN cuenta <= t_20_aux;
                ELSIF m_10 = '1' THEN cuenta <= t_25_aux;
                ELSIF m_20 = '1' THEN cuenta <= t_25_aux;
                ELSIF seleccionar_producto = '1' THEN cuenta <= espera;
                END IF;

            WHEN t_20 =>
                IF m_5 = '1' THEN cuenta <= t_25_aux;
                ELSIF m_10 = '1' THEN cuenta <= t_25_aux;
                ELSIF m_20 = '1' THEN cuenta <= t_25_aux;
                ELSIF seleccionar_producto = '1' THEN cuenta <= espera;
                END IF;

            WHEN t_25 =>
                IF seleccionar_producto = '1' THEN cuenta <= espera;
                END IF;

            WHEN t_5_aux =>
                IF m_5 = '0' THEN cuenta <= t_5;
                END IF;

            WHEN t_10_aux =>
                IF m_10 = '0' THEN cuenta <= t_10;
                ELSIF m_5 = '0' THEN cuenta <= t_10;
                END IF;

            WHEN t_15_aux =>
                IF m_10 = '0' THEN cuenta <= t_15;
                ELSIF m_5 = '0' THEN cuenta <= t_15;                    
                END IF;

            WHEN t_20_aux =>
                IF m_20 = '0' THEN cuenta <= t_20;
                ELSIF m_10 = '0' THEN cuenta <= t_20;
                ELSIF m_5 = '0' THEN cuenta <= t_20;
                END IF;

            WHEN t_25_aux =>
                IF m_20 = '0' THEN cuenta <= t_25;
                ELSIF m_10 = '0' THEN cuenta <= t_25;
                ELSIF m_5 = '0' THEN cuenta <= t_25;
                END IF;
        END CASE;
    END IF;
END PROCESS;


PROCESS (cuenta)
BEGIN
    CASE cuenta IS
        WHEN t_15 => 
            IF seleccionar_producto = '1' THEN insignia <= '1';
            END IF;
        WHEN t_20 => 
            IF seleccionar_producto = '1' THEN insignia <= '1';
            END IF;
        WHEN t_25 =>
            IF seleccionar_producto = '1' THEN gorro <= '1';
            END IF;
        WHEN OTHERS =>
            gorro <= '0';
            insignia <= '0';
    END CASE;
END PROCESS;
END maquina_exp
  • 1
    Possible duplicate of https://stackoverflow.com/questions/31138152/vhdl-state-machine-with-several-delays-best-approach/31139055#31139055 –  Dec 23 '17 at 12:16
  • 1
    What is a 30 inch counter and a 500 milli Hertz FPGA? You state machine has no start state. You should not implement a counter in a state machine. Use a separate counter stat is controlled by the state machine. – Paebbels Dec 23 '17 at 12:51
  • 1
    "Any idea how to do it?" has a yes or no answer, too broad and prone to opinions. Can you asks a [specific programming question](https://stackoverflow.com/help/how-to-ask) instead of a [subjective question](https://stackoverflow.blog/2010/09/29/good-subjective-bad-subjective/)? The latter better suited to https://electronics.stackexchange.com/questions/tagged/vhdl. @Paebbels - espera translates to wait a start state, waiting for one of m_5, m_10 or m_20. " can be used to mean seconds, accurate clocks developed to measure longitude. The as yet unimplemented counter likely driving m_5 etc. –  Dec 23 '17 at 17:44
  • 1
    The provided code doesn't analyze, having a spurious back tick after the semicolon in the use clause, missing a closing parenthesis before the last semicolon for the port declaration and a missing semicolon after the architecture end statement's maquina_exp. You can use a prescalar counter to allow counting second or five second intervals. –  Dec 24 '17 at 00:32

0 Answers0