Today I'm studying in the MIPS pipeline and finding out one interesting thing. Seeing the code below:
I1: lw $s1, 0($s3)
I2: add $s4, $s5, $zero
I3: beq $s1, $s5, 8
In order to reduce penalty of branch, we make compare two register data in ID stage. Making me confuse is that whether this condition is a kind of load use hazard or not? Does it cause a stall in pipeline?
I'm wondering whether there is a forwarding form MEM stage to ID stage to avoid pipeline stall in this case?
Because the textbook seems not mention it and I don't know how the exact MIPS works, I guess it won't cause a stall.
Thanks eveyone!!!
