How statements are executed concurrently in combinational logic using VHDL?

Question

I wonder how signal assignment statements are executed concurrently in combinational logic using VHDL? For the following code for example the three statements are supposed to run concurrently. What I have a doubt in is that how the 'y' output signal is immediately changed when I run the simulation although if the statements ran concurrently 'y' will not see the effect of 'wire1' and 'wire2' (only if the statements are executed more than one time).

entity test1 is port (a, b, c, d : in bit; y : out bit);
end entity test1;
------------------------------------------------------
architecture basic of test1 is
signal wire1, wire2 : bit;
begin
    wire1 <= a and b;
    wire2 <= c and d;
    y <= wire1 and wire2;
end architecture basic;

Consider each such statement as a process and look at https://stackoverflow.com/questions/13954193/is-process-in-vhdl-reentrant/13956532#13956532 — , Jan 30 '18 at 14:18
IEEE Std 1076-2008 11.6 Concurrent signal assignment statements "A concurrent signal assignment statement represents an equivalent process statement that assigns values to signals." e) "...if any expression (other than a time expression) within the concurrent signal assignment statement references a signal, then the process statement contains a final wait statement with an explicit sensitivity clause. The sensitivity clause is constructed by taking the union of the sets constructed by applying the rule of 10.2 to each of the aforementioned expressions. ..." — , Jan 30 '18 at 16:42

score 3 · Accepted Answer · answered Jan 30 '18 at 14:26

Since VHDL is used for simulating digital circuits, this must work similarly to the actual circuits, where (after a small delay usually ignored in simulations) circuits continously follow their inputs.

I assume you wonder how the implementation achieves this behaviour:

The simulator will keep track of which signal depends on which other symbol and reevaluates the expression whenever one of the inputs changes.

So when a changes, wire1 will be updated, and in turn trigger an update to y. This will continue as long as combinatorial updates are necessary. So in the simulation the updates are indeed well ordered, although no simulation time has passed. The "time" between such updates is often called a "delta cycle".

How statements are executed concurrently in combinational logic using VHDL?

1 Answers1