0

LB MIPS operation : link : http://www.ece.cmu.edu/~ece447/s13/lib/exe/fetch.php?media=mips_r4000_users_manual.pdf Page 549

32 vAddr ← ((offset15)16 || offset15...0) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
 pAddr ← pAddrPSIZE – 1 ... 3 || (pAddr2...0 xor ReverseEndian3)
 mem ← LoadMemory (uncached, BYTE, pAddr, vAddr, DATA)
 byte ← vAddr2...0 xor BigEndianCPU3
 GPR[rt] ← (mem7+8*byte)24 || mem7+8*byte...8*byte

Below is the c code :

//Defines for easier readability of registers
#define OPCODE ((curr_instr >> 26) & 0x3F) 
#define OPCODE_SPECIAL (curr_instr & 0x3F) 
#define OPCODE_REGIMM ((curr_instr >> 16) & 0x3F) 

#define SIGNEXD(val) ((val & 0x8000) ? ((val) | 0xFFFF0000 ) \
                                            : ((val) & 0x0000FFFF))
#define TARGET (SIGNEXD(curr_instr)<<2)
#define RS ((curr_instr>>21) & 0x1F)
#define RT ((curr_instr>>16) & 0x1F)
#define RD ((curr_instr>>11) & 0x1F)

 void lb()
 {
  uint32_t addr = CURRENT_STATE.REGS[RS] + SIGNEXD(curr_instr);
  uint32_t mem = mem_read_32(addr - (addr&0x3));

  mem = (mem >> ((addr & 0x3)*8));
  NEXT_STATE.REGS[RT] = (mem & 0x80) ? (mem | 0xFFFFFF00) : (mem & 0xFF);
  //NOTE: Exceptions ignored
  }

I don't understand why the operation of LB is coded as above ?

lul
  • 21
  • 1
  • 8
  • Why *wouldn't* it be coded that way in a MIPS emulator? Except for the terrible coding style of using global variables instead of function args instead of passing the instruction word as a `uint32_t`... – Peter Cordes May 18 '18 at 06:49
  • I don't understand what the lines in the operation mean...Any good tutorial ? sorry i'm just a beginner... – lul May 18 '18 at 06:53
  • Well, we can see from the C that [`lb` is a sign-extending byte load](https://stackoverflow.com/questions/7226147/clarifications-on-signed-unsigned-load-and-store-instructions-mips), unlike `lbu` (unsigned: zero-extend). The low 16 bits of the instruction word are a displacement from the base register. I'm not sure why all the endian stuff comes into the operation stuff in the MIPS manual, or why it would do a HALFWORD load; are you sure you got the right instruction? – Peter Cordes May 18 '18 at 06:56
  • Doesn't the MIPS manual itself describe the pseudocode it uses, and what things mean? – Peter Cordes May 18 '18 at 06:58
  • I got sth wrong, but updated. The code and the pseudocode are quite different here... Could you explain the pseudocode a bit... – lul May 18 '18 at 07:03
  • or is it possible to write several lines of code (each line of code corresponding to each line of operations in the manual) to explain... Thank you very much... – lul May 18 '18 at 07:09
  • `(mem7+8*byte)24 || mem7+8*byte...8*byte` looks like it might be describing the sign extension. I don't know the MIPS manual's notation. The rest of it looks fairly straightforward, except for the big/little endian setting reversing the order of byte addresses within a word. Pretty sure that's what the line between address-translation and load is doing. (MIPS can operate in big or little endian mode. The simulator C code is probably simulating big-endian only) – Peter Cordes May 18 '18 at 07:20
  • Hi, Thank you for the help. I still confused about pAddrPSIZE – 1 ... 3 ? – lul May 18 '18 at 07:45
  • Me too. It seems to be part of modifying the low bits of the address if little-endian, but I haven't fully understood what it's doing. – Peter Cordes May 18 '18 at 07:50
  • I felt for this lab it is better just see what it is general doing and then move on to the next one. self-learning computer arch from professor onur.any advice ? – lul May 18 '18 at 08:33

0 Answers0