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In a recent question (Difference in initializing a state machine between a simulator and synthesizer) I found out that simulators and sythesizers do not always treat VHDL code in exactly the same way. For example, when initialising a state machine using an enumerated type a simulator defaults to the enumerator's left hand value; however, it does not appear so clear cut as to the value a synthesizer defaults to.

Being relatively new to VHDL and FPGAs, it got me wondering as to whether there are other differences between the two that would be useful to know about. Does anyone know of any such differences that they would share? Even links to other places explaining such differences would be useful.

Thanks

Ron
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    This question might be better suited to https://electronics.stackexchange.com – scary_jeff May 22 '18 at 14:10
  • On the one hand, you can describe behavior that cannot be synthesized. On the other hand, you can write code that synthesizes but has a different behavior in simulation, because the used languages constructs are ignored by synthesis. You can write code that work in simulation, but cannot be mapped to your underlying hardware. In all these cases you create a mismatch between the synthesis model and the simulation model. – Paebbels May 22 '18 at 17:40
  • For enumerated types: You can force synthesis to use a binary encoding. Normally, you want that synthesis recognizes a special FSm pattern and treats the description as an FSM. Furthermore, you want synthesis to analyze and optimize the FSM. And you want it to choose the optimal implementation for your FSM. So synthesis will decide what encoding to use: binary, sequential, fast, gray code, johnson code, user code. Yes, with the last option, you can specify your own encoding. – Paebbels May 22 '18 at 17:46
  • This question is much too broad: There is no general answer to this question. It is a matter of reading the #$#%@ manual. Each synthesis tool supplier defines it's own set of synthesize constructs, which they describe in a user guide. Some other constructs are possible, but you should really follow the guide to be sure you get what you want (and even that may fail sometimes). – JHBonarius May 23 '18 at 08:56

1 Answers1

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I come from Verilog but about the same rules apply.

1/ Do not use any initialization, use a reset.
2/ Do not use sensitivity list. Use always @( * ) or always_comb
I don't know the VHDL equivalent of this one, but I assume somebody will point it out in a comment soon ;-)
3/ Never assume, always know what kind of logic will be generated. If you are not sure, use a different language construct or find out.
4/ Be fussy, meticulous, precise, excessively orderly, the best description is: be anal!

By the way I followed the mentioned post and was somewhat stunned by it. I'll be honest: I don't like VHDL for many reasons and thought the one asset of it was that errors like that where not possible because of the tight type & vector length checking. Obviously not, so the only remaining reason for using VHDL goes out the window for me.

Oldfart
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    Actually, as `all` in the sensitivity list was not implemented until VHDL-2008, some tools (like Xilinx ISE 14.7, required for all pre-7 series FPGAs) still don't support it. So sensitivity list is still required for portability. – JHBonarius May 22 '18 at 17:16
  • I also was surprised to discover, that many initializations *are* actually synthesizable (not the `initial` block, but registers/signal initialization). – Eugene Sh. May 22 '18 at 17:26
  • @EugeneSh. Yes, but you can read about the problems here: https://stackoverflow.com/questions/48915064/verilog-initialization-in-hierarchical-design/48916458#48916458. Experienced HDL programmers will tell you to avoid it if possible. Use a reset instead. – Oldfart May 22 '18 at 17:58
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    I consider myself quite an experienced VHDL programmer (10+ years experience in industry: Philips, ASML, NXP, Bosch) and I have been using initialization all the time. It works both with Intel Altera and Xilinx. The only problems I heard came from the ASIC world. – JHBonarius May 23 '18 at 08:54
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    I am also an experienced VHDL designer and strongly encourage the use of initialization values for registers **if the target technology supports it**. – Juergen May 23 '18 at 11:11