how to create a xored ring oscillator using VHDL

Question

I want to create xored oscillators using multiple inverters. The number of oscillator and inverter should be defined in generic. I have finished 1 oscillator but I don't know how to generate the same oscillator multiple times and let them xored. this is a part of my code:

    gen_ring_oscillator:

    for i in 1 to NUM_INVERTER-1 generate

    osc_chain(i)<= not osc_chain(i-1);
    end generate;



ring_oscillator:process(osc_chain, en_oc, osc_reset)
begin 

    if (osc_reset = '1') then
        osc_chain(0) <= '0';

    elsif (en_oc = '1') then

        osc_chain(0) <=  osc_chain(NUM_INVERTER-1);
        ro_out <= osc_chain(NUM_INVERTER-1);


    end if;

end process;

I have alreday used osc_chain as a signal between the inverters.

I don't understand the question. You have the code for one oscillator, why can you not put it in an entity/architecture and instantiate it multiple times? — Matthew Taylor, Jun 18 '18 at 07:59

JHBonarius · Answer 1 · 2018-06-18T11:12:32.173

By default VHDL assumes zero delay elements. As a result, the oscillation frequency will be 1/0 = error (infinitely large). This will cause an "maximum number of iterations reached" error

Thus you will have to configure the component delay manually, by adding after x ns with your assignment.

osc_chain(i)<= not osc_chain(i-1) after 10 ns;

More information can be found here and here.

Complete example (with some variation in delay):

library ieee;
use ieee.std_logic_1164.all;

entity ring_osc is
    port(clk_out : out std_logic);
end entity;

architecture rtl of ring_osc is
    signal osc_chain : std_logic_vector(2 downto 0) := (others => '0');
begin
    gen_inv: for i in 0 to 2 generate
        osc_chain(i) <= not osc_chain((i+1) mod 3) after (10 + i) * 1 ns;
    end generate;
    clk_out <= osc_chain(0);
end architecture;

Note: for a ring oscillator to work, you need an odd number of inverters.

how to create a xored ring oscillator using VHDL

1 Answers1