Can i assign 2 state out of bound accessed bits to 4 state variable?

Question

Should this produce x or 0 and thus the result be completely x or 0? Acc. to LRM if we access 2 state variable out of bound then it should be 0. Is it correct to assign 0 to r2.

module top;
    reg [1:0] r;
    bit [1:0] b;

    assign  r2= b[2:1] + b[3:2]; 
    initial begin
       $monitor(r2);
    end
endmodule

I have tried this on 4 simulators. 3 return 0; 1 returns an X. I don't know which is correct: the LRM gives an example using the `logic` type, but not the `bit` type as far as I can see. — Matthew Taylor, Jul 13 '18 at 07:51
I say I don't know which is correct, because it doesn't seem to be clear in the LRM (but I didn't read all 1275 pages!). I teach that an out-of-range index on an array returns the default value for the type, making 0 correct and X wrong. — Matthew Taylor, Jul 13 '18 at 08:01

score 3 · Answer 1 · answered Jul 13 '18 at 14:04

Reading from IEEE 1800-2012 Section 11.5.1:

The bit can be addressed using an expression that shall be evaluated in a self-determined context. If the bitselect address is invalid (it is out of bounds or has one or more x or z bits), then the value returned by the reference shall be x for 4-state and 0 for 2-state values. A bit-select or part-select of a scalar, or of a real variable or real parameter, shall be illegal.

As mentioned in the LRM, the result of out-of-bound selection should be default value. In your case of two state variable (bit), the value should be zeroed out.

The VCS 2017 migration guide also has bug fixes for bit select for parameters. I tried out the following code and found satisfactory results with a latest simulator:

module top;
    reg [1:0] r2;
    bit [1:0] b;

    assign  r2= b[2:1] + b[3:2]; 
    initial begin
      b = 1;
      #1;
      $display("r2 = %b b[3:2] = %b", r2,b[3:2]);
    end

endmodule

Note that the example is ran on different versions of simulator. Other simulators can behave differently.

Output VCS 2017:

bit [1:0] r2; bit [1:0] b; // --> r2 = 00 b[3:2] = 00

reg [1:0] r2; bit [1:0] b; // --> r2 = 00 b[3:2] = 00. VCS 2014 is having a bug where it is solving this equation with 4 state value.

bit [1:0] r2; reg [1:0] b; // --> r2 = 00 b[3:2] = xx. Here the x is optimized to the default value of bit.

reg [1:0] r2; reg [1:0] b; //--> r2 = xx b[3:2] = xx

Note that the result is always expected as 'x' when we are using part-select itself as 'x'.

A part-select that addresses a range of bits that are completely out of the address bounds of the vector, packed array, packed structure, parameter or concatenation, or a part-select that is x or z shall yield the value x when read and shall have no effect on the data stored when written.

The above one is again from same section from LRM.

Can i assign 2 state out of bound accessed bits to 4 state variable?

1 Answers1