Signal assignment in a clocked process happening instantly

Question

So I have a simple enough clocked process that assigns the value of one std_logic_vector to another.

capture_proc: process(clk) 
begin
    if rising_edge(clk) then
        captured_data <= sdram_din; 
    end if;
end process;

My problem is that on the rising edge of clk the value that is put into captured_data is readable by other processes on the same rising edge.

My understanding of signal assignment in sequential code is that in a simulation it actually happens right before the next trigger a clock cycle later. This is not what happens in my case as seen below.

In the following simulation I forced the value of sdram_din to 0x0000 on a falling edge and on the next rising edge the value assignment takes place. Why does the value appear instantly but not a cycle later?

Waveform

All of the code can be seen here.

Answer 1

My problem is that on the rising edge of clk the value that is put into captured_data is readable by other processes on the same rising edge.

(Emphasis is mine)
The waveform shown does not have the behavior. To show that you would need to add another signal, derived from captured_data using the same clock.

My understanding of signal assignment in sequential code is that in a simulation it actually happens right before the next trigger a clock cycle later.

I don't understand where this expectation comes from. The moment the clock rises the signal sdram_din is sampled. The same holds for all other signals which have the 'rising_edge(clk)` condition. The only think special is that all values are first sampled and only after all samples are taken are the values assigned.

Why does the value appear instantly

As I wrote above: after the signals are sampled they are assigned. Immediately. In a simulation no noticeable delay is present. (For details look up 'VHDL delta time'.) Any signal which is combinatorial derived from captured_data will appear also with no delay as in an ideal simulation there is no delay.