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i have wrote a simple PeekPokeTester testbench in chisel and it compiles and run successfully using verilator backend.
but now i want to pass some flags to verilator backend. in driver options there is a "--more-vcs-flags" option but there is not a similar thing for verilator. is there any way to change verilator flags or CFLAGS? to be more specific i want to simulate xilinx primitives as blackbox in chisel and i have to add something like "-y $VIVADO_INSTALL_DIR/data/verilog/src/unisims" to verilator compilation command
thanks

Amin Habibi
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There is an issue open for this subject on project : https://github.com/freechipsproject/chisel-testers/issues/148

FabienM
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  • Thanks but its about vcs and they have added options for vcs but there is no similar thing for verilator. Is theere any other way? – Amin Habibi Aug 21 '18 at 04:23
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    I asked a similar question here https://stackoverflow.com/questions/49638404/how-to-change-timescale-in-vcd-generated-by-chisel3-iotester . As I know, there is no solution for this moment. – FabienM Aug 21 '18 at 07:57