How to perform write back of dirty L1-L2 cache lines in ARMv8

Question

I'm looking for a way to flush the L1-L2 cache using a kernel module. Is there a way to completely flush the whole cluster cache (4 core configuration) or even better, write back the dirty cache lines into main memory?

score 0 · Answer 1 · answered Sep 12 '18 at 10:51

0

It sounds weird that you want to flush your caches from a kernel module. That should be done by the core-kernel part and as a driver you should not have to worry about that.

Is there any specific reason you need to do that in a driver?

answered Sep 12 '18 at 10:51

matthias.bgg

165
4

I want to achieve data coherency between the SoC and external devices. So if data in an allocated page are modified by X, i want to make sure that the changes will be visible to Y, which is outside the cache coherency of X – Κυριάκος Παρασκευάς Sep 12 '18 at 11:15
so why not just use the `volatile` keyword [(see here)](https://stackoverflow.com/questions/246127/why-is-volatile-needed-in-c?) ? It prevents data to be written to cache in first place – jonnyx Sep 20 '18 at 07:04
@jonnyx volatile keyword tells the compiler to reread data value instead of assuming that it has stayed the same. This is not what I want. – Κυριάκος Παρασκευάς Sep 21 '18 at 11:07

score 0 · Answer 2 · answered Sep 12 '18 at 14:01

0

I think you want to have a look at 3.9 of "Understanding the Linux Virtual Memory Manager" [1] from Mel Gorman. I think what you are looking for is flush_cache_page(...)

[1] https://www.kernel.org/doc/gorman/

answered Sep 12 '18 at 14:01

matthias.bgg

165
4

Nice one, but I cannot find an implementation for the Arm64 architecture, only for the older arm. Thanks a lot though. Things get complicated as there is a more sophisticated L2 cache controller present in Armv8 – Κυριάκος Παρασκευάς Sep 13 '18 at 13:23
Fair enough, but there are other methods implemented for arm64, did you had a look at __flush_dcache_area(kaddr, size)? – matthias.bgg Sep 23 '18 at 10:45
Yes I did, from what i read, it flushes a page, or an area, from L1 cache, and sends it to the L2 cache. – Κυριάκος Παρασκευάς Sep 24 '18 at 14:04

score 0 · Answer 3 · answered Nov 27 '18 at 17:37

Well it seems that it is actually different the way that the caches are flushed in different architectures. Nevertheless, I didn't find an implementation that works. BUT, what I did was to find the Page table entry (PTE) of the particular page that I want to flush, and changed the memory attributes to Non-Cacheable. Then, the data went directly to the DRAM. (ARMv8) Cheers

How to perform write back of dirty L1-L2 cache lines in ARMv8

3 Answers3