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Questions tagged [armv8]

This tag is for questions regarding specifically version 8 of the ARM architecture - 32-bit or 64-bit. Questions about the 64-bit ARM execution state or instruction set should be tagged with [arm64].

Version 8 of the ARM architecture introduced a new 64-bit execution state (AArch64) with a new 64-bit instruction set (A64) as well as retaining and extending the existing 32-bit execution state (AArch32) and its instruction sets A32 ("ARM") and T32 ("Thumb").

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Why might one use the xzr register instead of the literal 0 on ARMv8?

I was reading the SVE whitepaper from ARM and came across something that struck me as odd (in a non-SVE example): mov x8, xzr I didn't know what this xzr register was, so I looked it up and found some content from ARM stating that it was, in many…
OMGtechy
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What's the difference between MOV, MOVZ, MOVN and MOVK in ARMv8 assembly?

I was using a disassembler when I came across MOVZ and was a bit confused, since I had only used MOV before. The ARMv8 ISA manual explains of course all the details, and that MOV is an alias for the other three depending on the context, but maybe…
Ciro Santilli
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How to determine ARMv8 features at runtime on iOS?

I am trying to determine when optional ARMv8 cpu features are available on iOS at runtime. On OS X desktops, like i686, x86_64, PPC and PPC64 we can use sysctl. See, for example, PR 3108, SIGILL-free processor capabilities detection on MacOS X. The…
jww
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LDUR and STUR in ARM v8

I've had a couple of courses that touched on ARMv8 assembly, but both teachers described LDUR/STUR instructions a different way and now I've become pretty lost. Can someone help to clarify? If I had the instruction: LDUR R3, [R1, #8] I'll be…
Plutonium
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Division by zero not causing runtime exception on Nvidia Jetson

I'm not very familiar with the internal details of ARM processors, but I do not understand the following behaviour on my Nvidia Jetson Nano dev board. C code sample ... //main.c #include int main() { int fred = 123; int i; …
user5069935
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Avoiding hard-number shift of flexible second operand in ASM

This question pertains to the ARM assembly language. My question is whether it is possible to use a macro to replace the immediate value in the ASM code to shift a register value so that I don't have to hard-code the number. I'm not sure whether the…
Jay
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How to debug an aarch64 translation fault?

I am writing a simple kernel in armv8 (aarch64). MMU config: 48 VA bits (T1SZ=64-48=16) 4K page size All physical RAM flat mapped into kernel virtual memory (on TTBR1_EL1) (MMU is active with TTBR0_EL1=0, so I'm only using addresses in 0xffff< addr…
maxbc
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ARMv8.3 meaning of rcpc

With ARMv8.3 a new instruction has been introduced: LDAPR. When there is a STLR followed by a LDAR to a different address, then these 2 can't be reordered and hence it is called RCsc (release consistent sequential consistent). When there is a STLR…
pveentjer
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Why does hint::spin_loop use ISB on aarch64?

In std::hint there's a spin_loop function with the following definition in its documentation: Emits a machine instruction to signal the processor that it is running in a busy-wait spin-loop (“spin lock”). Upon receiving the spin-loop signal the…
Błażej Michalik
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What is the purpose of Thread ID registers like TPIDR_EL0/TPIDR_EL1 in ARM?

According to ARM documentation, the thread ID registers like TPIDR_EL0 or TPIDR_EL1, Provide locations to store the IDs of software threads and processes for OS management purposes. These registers have no effect on processor behavior. Why would…
Guerlando OCs
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How this simple paging in ARMv8a works

According to the ARM manual: In the case of a 4kB granule, the hardware can use a 4-level look up process. The 48-bit address has nine address bits for each level translated (that is, 512 entries each), with the final 12 bits selecting a byte…
Paprika
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AOSP Build TARGET_PRODUCT fails

I'm trying to build an external tool with AOSP. My OS is Linux, Distribution ArchLinux (i3wm), but to compile AOSP I use Ubuntu in Docker (https://android.googlesource.com/platform/build/+/master/tools/docker) First step: # init repo repo init -u…
VasileM
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Linux syscall conventions for Armv8

Does anyone know where i can find the conventions for Linux syscalls in ArmV8? What register parameter must be passed in and where are return values stored.
KAM
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ARMv8 backward compatibility with ARMv7 (Snapdragon 820 vs Cortex-A15)

I see that ARMv8 is merely an extension of ARMv7 architecture and all code compiled on ARMv7 should run on ARMv8. I am interested in the backward compatibility of ARMv8 to ARMv7. Will code that was compiled on ARMv8 run on ARMv7? I have a particular…
Kozuch
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What new instructions does ARMv8-M Baseline provide over ARMv6-M?

In 2016, ARM introduced the ARMv8-M architecture as an upgrade to the popular ARMv6-M (Cortex M0/M0+/M1) and ARMv7-M (Cortex M3/M4/M7) architectures. The ARMv8-M architecture is again split into a Baseline profile seen as a continuation of the…
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