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In std::hint there's a spin_loop function with the following definition in its documentation:

Emits a machine instruction to signal the processor that it is running in a busy-wait spin-loop (“spin lock”).

Upon receiving the spin-loop signal the processor can optimize its behavior by, for example, saving power or switching hyper-threads.

Depending on the target architecture, this compiles to either:

That last one has got my head spinning a little bit (). I thought that ISB is a lengthy operation, which would mean that, if used within a spin lock, the thread lags a bit in trying to detect whether the lock is open again, but otherwise there's hardly any profit to it.

What are the advantages of using ISB SY instead of a NOP in a spin loop on aarch64?

Błażej Michalik
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    Good question. AArch64 also has a YIELD instruction but the description of it in the Architecture Reference Manual doesn't really make sense. It speaks of performing a task that could be "swapped out" or that the PE could "suspend and resume multiple software threads". But those seem like OS functions. I don't see how a hardware instruction could accomplish that, unless it was actually a trap, and there's no indication of that. Its pseudocode description is `Hint_Yield();` but that function is not defined in the manual. – Nate Eldredge Jan 22 '22 at 05:08
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    @NateEldredge: That description sounds like it was written in case anyone wants to design a core with coarse-grained multithreading that does switch-on-stall (https://en.wikipedia.org/wiki/Multithreading_(computer_architecture)#Coarse-grained_multithreading), unlike SMT (e.g. AMD Zen, or Intel Hyperthreading) or an in-order barrel processor. On a core like we're used to with mainstream Intel/AMD CPUs, yes, that description for a YIELD instruction makes no sense. (Although presumably you're handle it like x86 PAUSE, just yielding the front-end to the other hardware thread(s).) – Peter Cordes Jan 22 '22 at 08:01

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I had to dig into the Rust repository history to get to this answer:

The yield has been replaced with isb in c064b6560b7c:

On arm64 we have seen on several databases that ISB (instruction synchronization barrier) is better to use than yield in a spin loop. The yield instruction is a nop. The isb instruction puts the processor to sleep for some short time. isb is a good equivalent to the pause instruction on x86.

[...]

So essentially, it uses the time it takes for an ISB to complete to pause the processor, so that it wastes less power.

Peter Cordes explained it nicely in one of his comments:

ISB SY doesn't stall for long, just saves a bit of power vs. spamming loads in a tight loop.

Błażej Michalik
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