VHDL Pulse Generator with loop/after

Question

I have been trying to build a pulse generator to, let's say, detect when a signal has fallen. I have tried different ways to build this pulse generator using processes: my simulation hangs.

I'm posting this question, not so much seeking the code for a pulse generator, but rather hoping for an explanation of why this approach does not work. I'm trying to make the jump from sequential languages (like C++, etc) to VHDL and I'm running into this invisible conceptual wall. Thanks in advance.

library ieee;  
use ieee.std_logic_1164.all;  

entity puls_on_FE is  
    port (signal_in : in  std_logic; pulse_out : out std_logic);  
end puls_on_FE;

architecture behavior of puls_on_FE is  
signal epoch: std_logic := '0';  
begin  
    process (signal_in)
    begin
        if falling_edge(signal_in)then
            pulse_out <= '0';
            wait1:  loop   --using loop because an after by itself hangs the sim too
                exit when epoch = '1';
                epoch <= '1' after 5 ns;  
            end loop wait1; --expect loop to execute once and exit after 5ns
            pulse_out <= '1';
        end if; 
    end process;
end behavior;

See the explanation [in this answer](https://stackoverflow.com/questions/50158190/sequential-execution-in-process-statement-in-vhdl/50163596#50163596). Signal values aren't updated during the execution of a process, you're synthesis ineligible loop statement sequence of statements executed repeatedly can't see the update on epoch scheduled for a future simulation time. Note there is nothing assigning epoch to a value other than '1' here. — , Sep 27 '18 at 23:32

score 0 · Accepted Answer · answered Sep 28 '18 at 15:03

Signals dont get updated until a process suspends, either by hitting a wait statement or getting to the end of the process when it has a sensitivity list. In your example, you enter a loop that has no mechanism to wait for any length of time. In each loop iteration you assign

epoch <= '1' after 5 ns;

because you are not waiting inside the loop, each iteration takes 0 deltas and time never increments by any deltas. (btw, you're not allowed to wait here because the process has as sensitivity list)

I suggest you step back from coding, and get do more drawing. What circuit do you intend this code to create? can you draw the circuit? Because VHDL is a description language you need to have an understanding of what circuit you are trying to create, rather than writing code that you think might emulate some sort of circuit.

I also question the need for the "after" assignment. You cannot synthesise a real circuit using "after" - they are only there to emulate inertial delays of signals and only apply usefull to simulation.

Thanks Tricky. I think drawing the circuit first and then coding is the answer. I've also seen several other issues in my code since then: for example, that the pulse_out is undefined in all cases unless there is a falling_edge of signal_in (because the else is still inside the process which is watching for changes on signal_in). Since I posted the code, I have figured out how to implement this pulse generator. — Gaspar Dellafofoo, Sep 28 '18 at 21:27

VHDL Pulse Generator with loop/after

1 Answers1