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I have to create two vcd files. One which starts at zero time and ends when a specific signal changes, and one which start right after.

Is it possible to do it with verilog?

Sara p
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The Verilog standard does not provide a way of doing this in one simulation. Your first simulation would run up until the specific signal changes creating your first VCD file. Your second simulation would have to start dumping to the second VCD file when the specific signal changes.

Some tools, like ModelSim/Questa, provide Tcl command line options for dumping to multiple VCD files. You would turn off dumping to the first VCD file at same time start dumping to the second VCD file. Please read your tools user manual.

dave_59
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  • Hi Dave, is this true for SystemVerilog as well? Modelsim suggests to use $fdumpfile to save more than one vcd (even if I still hadn't managed to successfully add waves to the second one), – a_bet Jun 27 '22 at 13:04
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    Should not matter if this is Verilog or SystemVerilog. – dave_59 Jun 27 '22 at 14:29
  • Ok, I'm wrapping my mind around it. In Questa you can use $fdumpfile(filename),, $fdumpall(filename) etc.. I am nearly there: I am just having troubles with: $fdumpvars( levels, {, module_or_variable } , filename) as I am not able to dynamically pass a string filname variable, but only hardcoded "path/to/filename.vcd" – a_bet Jun 28 '22 at 13:44
  • PS. The error is: # ** Error (suppressible): (vsim-PLI-3111) $fdumpvars : Last argument must be a filename. – a_bet Jun 28 '22 at 13:50
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    You should ask this as a separate question and show the code you are using. – dave_59 Jun 28 '22 at 16:08
  • See https://stackoverflow.com/questions/72799240/systemverilog-questasim-pass-string-to-fdumpvars-to-save-multiple-vcd-files – a_bet Jun 29 '22 at 09:45