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I have a confusing Verilog error that is coming up as I am trying to make a 5 bit 2x1 MUX using STRUCTURAL code and I can't seem to find any info on why my code would be showing up wrong. The error is:

error: Expression width 5 does not match width 1 of logic gate array port 1.

I know that it is talking about one of my inputs but I don't know which one is in port 1. But based on how the rest of the code is laid out, I'm pretty sure that all of 5bit wide inputs are matching with 5bit wires and with the 5bit output. Any help would be appreciated!

For reference here is my .v and tb.v

.v: {module mux_2x1_5bit(in1, in2, gate, out);

input [4:0] in1, in2;
input gate;
output [4:0] out;

wire [4:0] a, b;

and #4 and1(a, {5{gate}}, in1);
and #5 and2(b, {5{~gate}}, in2);
or #4 or1(out, a, b);

endmodule

tb.v:

module mux_2x1_5bitTEST();

wire [4:0] out;
reg [4:0] in1;
reg [4:0] in2;
reg gate;

mux_2x1_5bit DUT(in1, in2, gate, out);

initial
begin
    in1 = 5'b00000;
    in2 = 5'b00010;
    gate = 0;

    #20 in1 = 5'b00001;
    #20 gate = 1;
    #20 in2 = 5'b10101;
    #20 in1 = 5'b01101;
    #20 gate = 0;

end

always @(in1 or in2 or gate)
    #1 $display("| gate = %b | in1 = %b | in2 = %b | out = %b |",  gate,   in1,   in2,   out);

endmodule
Barnabas Bullion
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1 Answers1

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The problem is in here:

and #4 and1(a, {5{gate}}, in1);
and #5 and2(a, {5{~gate}}, in2);
or #4 or1(out, a, b);

The inputs and output of and gate only have the width is 1, but in here your inputs are 5. To fix this you can do like this:

assign a = {5{gate}} & in1;
assign b = {5{~gate}} & in2;
assign out = a | b;

or you can separate your inputs by 1 width if you wanna use and like this:

and and_a_1(a[0],gate,in2[0]);
and and_a_2(a[1],gate,in2[1]);
...
and and_a_i(a[i],gate,in2[i];
thangpx1706
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