Verilog - increment local parameter in generate block

Question

I'm getting an error in my Verilog generate block, on the line where it says j = j+1; stating `j is an unknown type'

genvar i;
generate
    localparam integer j = 0;
    for (i = 0; i < BUFFER; i=i+1) begin
        if((i%DATA_WIDTH) < (KERNEL_SIZE-1)) begin
            assign o_input_matrix[((j+1)*DATA_WIDTH)-1:j*DATA_WIDTH] = 
buffer[((i+1)*DATA_WIDTH)-1:i*DATA_WIDTH];
            j = j+1;
        end
    end
endgenerate

BUFFER, DATA_WIDTH, and KERNEL_SIZE are local parameters I have in my module.

I've been looking at ways I could have a 2nd parameter in my generate block, I've found out that I can only use genvar variables in a for loop, so I couldnt make a 2nd genvar variable for j.

I came across this question: Incrementing Multiple Genvars in Verilog Generate Statement

I tried basing my code of the 2nd answer, but my situation is slightly different because I'm only incrementing it in an if statement.

Any help would be appreciated.

score 0 · Accepted Answer · answered Mar 29 '19 at 19:17

0

You are going to have to make a function to define the value of j.

genvar i;
for (i = 0; i < BUFFER; i=i+1)
   if((i%DATA_WIDTH) < (KERNEL_SIZE-1)) begin
      localparam j = func(i);
      assign o_input_matrix[((j+1)*DATA_WIDTH)-1:j*DATA_WIDTH] = 
buffer[((i+1)*DATA_WIDTH)-1:i*DATA_WIDTH];
        end
    end
function integer func(integer ii);
   for (ii = 0;ii < BUFFER; ii++)
     if ((ii %DATA_WIDTH) < (KERNEL_SIZE-1)) ii++;
endfunction

Didn't try this, but hope it gets you close to what you want.

answered Mar 29 '19 at 19:17

dave_59

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Thanks, @dave_59, I think I managed to use a function to do the mapping I need. It's difficult for me to test whether this solution works, as I am getting a runtime error, is there any way to display the parameters in the generate block? I tried using $display, but I don't think I can use it in a generate block. – Physco111 Mar 30 '19 at 15:33
I don't know how a generate block would jive you a runtime error? What does it say? You can put `initial $display(parameters)` inside the generate assuming that comes before your runtime error. (SystemVerilog allows you to put $info as an elaboration message) – dave_59 Mar 30 '19 at 17:08

Verilog - increment local parameter in generate block

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